Oasys’ product, RealTime Designer, is claimed to be 10x-60x faster than the competition. Among other things, it uses AIG-based optimization. This technology is best illustrated by UC Berkeley’s ABC synthesis: several FPGA startups reported that ABC boosted significantly the speed, capacity, and quality of their synthesis engines. No question that Oasys’ synthesis is competitive, at least in the FPGA world.

Xilinx is an investor into Oasys, and it has been toying with their synthesis technology for at least a year, so it’s not like they just discover each other. Xilinx has to close a software technological gap with respect to its closest competitor, Altera, and a fast, high capacity synthesis will certainly help.

Synthesis speed is key here. Until recently FPGA design was mostly an iterative process: synthesize, simulate, and debug (i.e., change in the RTL) until the performances and functionality of the design were satisfactory. That trial-and-error approach becomes impractical as the size of FPGA devices is increasing to the point that one single iteration takes hours, if not a day. Having a 10x speedup in synthesis means you can restore that familiar design iteration for a few more years.

Verification has become a bottleneck in FPGA. Simulating is used and will still be used in the future. But FPGA’s complexity requires a more complete verification methodology, like formal verification. However formal verification has trouble addressing optimization techniques heavily used in FPGA synthesis, like retiming and state re-encoding. An ABC-like optimization engine comes with a built-in formal verifier that can check independently the correctness of every incremental optimization steps performed during the optimization run. The correctness of the resulting netlist comes with a very high degree of confidence, and only the RTL description needs to be simulated.

Xilinx’ customers will benefit from that technology, and catch up with Altera’s synthesis. As for the EDA vendors selling their own FPGA synthesis, they all use or will use some flavor of AIG-based optimization. Differentiation will be done on the smartness of the high-level optimization –datapath, IPs–, the user experience (GUI), the integrated verification environment (still to be demonstrated), and of course the bottom-line: QoR –clock cycle, area, and power. The race is on.

Related posts:

1. What to read in Xilinx’ and Altera’s third quarter results
2. How can Xilinx improve its bottom line
3. Is FPGA a sustainable market for EDA?

Comparing the yearly fiscal exercises directly would be biased (Xilinx’ fiscal year end on March 31^st, and Altera’s fiscal year on Dec 31^st). Instead we can look at a quarter by quarter comparison, even though that can be too low a level. Better is to look for ttm (trailing twelve months) comparison to smooth out the local variations.

Source: Yahoo! Finance. All figures in thousands.

One can see that Altera’s operating margin is overall better. Also in their respective Q3’09 revenue reports, Xilinx expects its Q4’09 gross margin to improve to 62-63%, and Altera sees his to be 67-68%.  So a 3-4% operating margin gap will remain, which is significant.

On the other hand, Xilinx quotes 3145 full time employees, and Altera 2760. This means that a Xilinx employee brings back revenue about 26% higher than an Altera employee! So it all boils down to the question: how can Xilinx be more cost efficient?

One of the differences is the way software is developed. Altera’s software is mostly done in their technology center of Penang, Malaysia, with a very small core technology group in Toronto, Canada. Xilinx’s software team is mostly in the US, and only 5% of the team is in their R&D facilities in Hyderabad, India. A back-of-the-envelop calculation shows that if Xilinx had the same software team but with a US/India ratio 1/3-2/3, which is a healthy ratio for a company that can leverage its India facility, Xilinx would improve its operating margin by one point.

If you extend the same reasoning to whole R&D –not only software–, then it is clear that Xilinx can get the upper hand. Looking at the R&D job listings, it is also clear that Xilinx is moving into that direction. The question then is whether Xilinx has the structure and the drive to achieve such a transformation successfully.

Related posts:

1. What to read in Xilinx’ and Altera’s third quarter results
2. Who should worry about Xilinx and Oasys partnership?

Source: Xilinx and Altera financial reports, and Yahoo! Finance

Xilinx’ quarterly income of $64M (0.23$/share) beats Wall Street’s expectation of 0.19$/share. Altera’s quarterly income of $56.7M (0.19$/share) meets Wall Street’s expectation. Both companies expect a 6-10% revenue increase for Q4’09 from previous quarter. Xilinx expects its Q4’09 gross margin to improve to 62-63%, and Altera sees his to be 67-68%.

Both companies are benefiting equally of an improving economy. Altera is seeing a large part of its revenue coming from new products (60% for Q3’09), as opposed to Xilinx (31% in Q3’09).

I would give a slight edge to Altera, given its recent offer of high-performance new devices, and its operation margin consistently ahead of Xilinx’. One day Xilinx should be able to close the 3-4% operation margin gap it has with Altera, but until then it will not be as efficient and dynamic as Altera. I will discuss in another post how Xilinx can close this gap.

Related posts:

1. How can Xilinx improve its bottom line
2. Who should worry about Xilinx and Oasys partnership?