Olivier Coudert on October 30th, 2012

Last week I was invited in Cambridge, UK, to participate to a panel at the FMCAD conference (Formal Methods in Computer-Aided Design). The subject: “Model Checking in the Cloud”.  With another four people, we discussed the questions laid out by the panel moderator: How can model checking leverage the advantages of distributed and multi-core systems […]

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Olivier Coudert on August 27th, 2011

So you got the news: Calypto acquired Catapult-C, the ESL synthesis tool from Mentor Graphics. Calypto has been into low power (using notably sequential optimization techniques) and sequential verification for a while. And the company has always been very close to Mentor Graphics: it had integrated its verification tool with Catapult-C as early as 2005. […]

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Olivier Coudert on August 16th, 2010

Systems on Chip (SoCs) integrate increasingly complex hardware features with even more complex software applications, which makes validating SoCs a challenging task. FPGA-based prototyping has become an increasingly popular way of validating SoCs, for good reasons: FPGA devices have enough capacity to fit complex ASICs, and run fast enough to interact with real world interface […]

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Olivier Coudert on April 20th, 2010

A FPGA company makes revenue with the hardware: it sells its device, and gives away its design tools –synthesis, place-and-route. Yet the EDA industry has had success with its own (non-free) FPGA synthesis solutions. For good reasons: in its days, Synplicity’s Synplify was the best FPGA synthesis out there. Synopsys acquired Synplicity two years ago, […]

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Olivier Coudert on February 21st, 2010

My last post must have struck a nerve. In this post I ask whether fundamental innovation stalled in formal verification, and I speculate which area the next technological leap will come from. This post received some quite interesting comments. It also brought a counter point by Brian Bailey, partially motivated by his business partnership with […]

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Olivier Coudert on January 24th, 2010

We all know that functional verification is the costliest and most time-consuming aspect of ASIC design –about 50% of the total cost, and from 40% to 70% of the total project duration. And we all know that simulation is by far the prevalent verification method, even though it is inherently incomplete due to an input […]

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Olivier Coudert on November 6th, 2009

ICCAD’09 was a fairly good vintage. It started Monday morning with an excellent keynote from Hamid Pirahesh about cloud computing. The same day in the afternoon, a more EDA-focused discussion was initiated by Jim Hogan and Paul McLellan (slides can be found here), asking the question “What EDA needs to change for 2020 success?” Paul […]

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