Oasys’ product, RealTime Designer, is claimed to be 10x-60x faster than the competition. Among other things, it uses AIG-based optimization. This technology is best illustrated by UC Berkeley’s ABC synthesis: several FPGA startups reported that ABC boosted significantly the speed, capacity, and quality of their synthesis engines. No question that Oasys’ synthesis is competitive, at least in the FPGA world.

Xilinx is an investor into Oasys, and it has been toying with their synthesis technology for at least a year, so it’s not like they just discover each other. Xilinx has to close a software technological gap with respect to its closest competitor, Altera, and a fast, high capacity synthesis will certainly help.

Synthesis speed is key here. Until recently FPGA design was mostly an iterative process: synthesize, simulate, and debug (i.e., change in the RTL) until the performances and functionality of the design were satisfactory. That trial-and-error approach becomes impractical as the size of FPGA devices is increasing to the point that one single iteration takes hours, if not a day. Having a 10x speedup in synthesis means you can restore that familiar design iteration for a few more years.

Verification has become a bottleneck in FPGA. Simulating is used and will still be used in the future. But FPGA’s complexity requires a more complete verification methodology, like formal verification. However formal verification has trouble addressing optimization techniques heavily used in FPGA synthesis, like retiming and state re-encoding. An ABC-like optimization engine comes with a built-in formal verifier that can check independently the correctness of every incremental optimization steps performed during the optimization run. The correctness of the resulting netlist comes with a very high degree of confidence, and only the RTL description needs to be simulated.

Xilinx’ customers will benefit from that technology, and catch up with Altera’s synthesis. As for the EDA vendors selling their own FPGA synthesis, they all use or will use some flavor of AIG-based optimization. Differentiation will be done on the smartness of the high-level optimization –datapath, IPs–, the user experience (GUI), the integrated verification environment (still to be demonstrated), and of course the bottom-line: QoR –clock cycle, area, and power. The race is on.

Related posts:

1. Is FPGA a sustainable market for EDA?
2. How can Xilinx improve its bottom line
3. What to read in Xilinx’ and Altera’s third quarter results

In a world where FPGA software design is expected to be free (or very cheap, compared to it ASIC counterpart), is there still a market for EDA companies to sell their FPGA solutions? Synplicity stopped growing after it built its success on FPGA synthesis. Is that the fate of EDA for FPGA?

There are several forces at play here: device complexity, software complexity, and know-how.

The complexity of FPGA starts to rival that of ASIC’s. The largest FPGA devices contain 100,000’s of LUTs and registers, 1000’s of DSP components, and are equivalent to 1+ million gate designs. The increasing device size requires faster synthesis and larger capacity. It also strains verification because simulation costs are augmenting accordingly. The days were a designer could complete her FPGA project with a simple write-RTL/synthesize/simulate/fix iterative flow are gone.

FPGA companies differentiate with their devices’ speed, capacity, and power consumption. But beyond the raw hardware features, software to design FPGA has become a key for success. Altera learnt the lesson the hard way 10 years ago when it released software that was not ready: Altera quickly lost its top customers to Xilinx, while it could have become the undisputed #1 FPGA vendor. Some FPGA startups in the past could not get off the ground because they fail to deliver good synthesis for their device. Closer to us, we have heard about Tabula’s chronic problems to bring up its synthesis before it finally announced its device earlier this year. And Abound Logic’s huge netlist has stretched the capacity of today’s FPGA synthesis.

Altera has now a software powerhouse, and is meticulous about its software design and testing. Xilinx is currently going through a major overhaul of its software to catch up with its main competitor. There is no question that software is taken very seriously by the two vendors –they both have a couple hundreds engineers dedicated to provide customers with a full design tool suite.

So does EDA has any future in FPGA synthesis? There will always be FPGA startups looking for an OEM with Synopsys and Mentor, but this is not enough. The EDA industry must showcase a comprehensive FPGA development environment that will cover design, synthesis, and verification:

• Verification is becoming ever more costly for FPGAs, as it already is for ASICs. Formal verification for FPGA is still embryonic –FPGA synthesis uses retiming and FSM re-encoding that makes formal verification quite difficult.
• Synthesis of complex systems with a large IP spectrum is an area of expertise that EDA must leverage. Also EDA could provide a much-needed improvement in power management.
• As for design, EDA must seize on the FPGA community’s ability to adopt new methodologies much faster than the ASIC community. ESL, SystemC, and C/C++ as hardware description languages are the right direction.

If EDA wants to compete with the few hundred software engineers of Xilinx and Altera, it needs to deliver a best-in-class and innovative FPGA design environment. Else it will end up as a no-growth by-product of ASIC synthesis.

Related posts:

1. Why FPGA startups keep failing
2. The formal verification market is still untapped
3. Who should worry about Xilinx and Oasys partnership?

I will focus on three items necessary for power gating: (1) the FSM that controls the sleep and wake-up sequences; (2) the retention flops used to restore the state of the device when it is awakened; and (3) the correctness of the power gating implementation. Items (1) and (2) are manually done via UPF/CPF directives and FSM hand-coding. Item (3) is carried out with customer-specific methods, even though the use of CPF together with Conformal produces a more solid verification flow.

Sleep/wake-up protocol synthesis

Items (1) and (2) must really be considered together to answer the following question: how to implement a sleep and wake-up sequences that use retention flip-flops to resume the device’s state? It is clear that answers to that question are different tradeoffs between the number of retention flops and the length of the sequences. The more retention flops, the shorter the sequences are, but the higher the price in terms of area and residual leakage power. In essence, one would like to be able to explore the possible tradeoffs and pick the best compromise, depending on the application. Also from the designer point of view, one should not have to manually decide which flip-flops must be shadowed, nor one should have to hand-code the FSMs for the sleep and wake-up sequences.

Instead, one should be able to synthesize the retention flip-flops and the sleep and wake-up FSMs directly from a power state table –what I call sleep/wake-up protocol synthesis. I would propose an extension of the power state table so that transitions can also be labeled with constraints: an upper bound on the sequence length (in terms of number of clock cycles or milliseconds), and an upper bound on the area taken by the retention flops (actual area or as a percentage of the element area). This way the designer can concentrate on the power management strategy and explore different tradeoffs, instead of having to figure out the implementation itself.

Sleep/wake-up protocol synthesis is no small task. I would look into information relevance and functional dependency analysis to derive a candidate set of retention flops. Compression and encoding methods can then be used to reduce this set. The final FSM synthesis would implement the decoder. Looking into techniques coming from DFT, simulation, and formal verification could prove very helpful.

Sleep/wake-up protocol verification

Item (3) is verifying the correctness of the power gating implementation. There are two aspects here. One is purely physical, and consists of checking that level shifters, isolation cells, and power switches have been properly inserted. The insertion of these cells can be automated, and verifying that their insertion obey basic physical rules in not a problem (this is supported for both UPF and CPF).

The main issue is to verify the functional correctness of the sleep/wake-up sequences, namely that the device meets some operational expectation once re-activated (e.g., the pre-sleep state is fully restored). Intensive simulation will give some coverage, but cannot be exhaustive in general. Sequential formal verification or property checker can then be used for a proof of correctness. For instance the property would go something like “if the device goes to sleep and then is re-activated, its state is fully restored to its pre-sleep state in less than one second”. To be manageable, such a property must be broken down in smaller or more abstract expressions. The same synthesis system that takes care of items (1) and (2) should generate the properties that a 3^rd party property checker can independently verify to guarantee the correctness of the sleep/wake-up protocol. This is no different than a RTL synthesis tool giving hints to an equivalence checker to simplify the proof.

Conclusion

Given the complexity of today’s sleep/wake-up protocol design and verification, it is somewhat surprising that no EDA tool is really tackling the problem today. Is it because of user unawareness, or because of the size of the challenge? Regardless of the reason, the first company to offer sleep/wake up protocol synthesis and verification will make a major impact in the low power design community.

Related posts:

1. Automated low-power design flow is up for grabs (Part I)
2. Is FPGA a sustainable market for EDA?
3. The formal verification market is still untapped

For mobile products, leakage power (the power consumed when the device is on but idle) has become a dominant factor, as opposed to dynamic power (the power resulting from the actual activity of the device, e.g., during a call for a cell phone). In that context, power gating is a key for extended battery life. Under some condition (e.g., the “on/off” button is pressed, or the device has been unused for some time), the device goes to sleep: it powers down most of its elements and preserves enough information to restore the state it was in before going to sleep. Under another condition (e.g., the “on/off” button is pressed again), the device powers back up and resumes its course as it was right before going to sleep.

UPF (Unified Power Format, endorsed by Synopsys, Mentor, and Magma) has been introduced to describe the power supply distribution and its control. With UPF one can specify power domains (a set of design elements that share a power supply), and a power state table that captures the transitions between the power domains. For instance it is used to describe under which conditions the device goes to sleep, under which conditions it must be powered back up, and what happens whenever the device transitions between these modes. UPF allows the designer to specify retention flops, level shifters, and isolation cells, all necessary items for multiple voltage designs and power gating. CPF, promoted by Cadence, is another format that is used to describe similar power management schemes.

Low power has been a subject of attention from chip designers and EDA for more than 10 years. Indeed, a lot of improvement has been done. New techniques have been introduced, and most are now common practices and relatively well automated –clock gating, multiple Vt cells, multiple voltages.

Despite these progresses, low power-centric design flows remain a very labor intensive process. Even if UPF/CPF can be used to describe transitions between different power modes, it is up to the designer to manually write the controller (as a FSM) that implements the transitions, and it is up to the designer to determine which information must be preserved (the retention flops) in order to resume the application to its pre-sleep state.

Also low-power designs create new challenges for functional verification. For instance, after going to sleep, the device must be able to resume without loss of information. Since the sleep and power-back-up sequences take several clock cycles, simple equivalence checking is not sufficient. Sequential verification or intensive simulation is needed. Cadence did a relatively good job in tying CPF to its Formal Verification solution (Conformal), Mentor and Synopsys have some reasonable flow for UPF, but verifying the correctness of a power state table FSM is still a very manual and error-prone process.

EDA stands for bringing automation to design flows, and low power design could use some help. In Part II, I will show how some parts of the low power design flow can be automated.

Glossary

Sleep mode: the power state a device is in when it is not actively used by the user. In that state most of the device is shut down, but is ready to wake up when the user needs it.

Active mode: the power state a device is when it is fully active (e.g., making a call with a cell phone).

Power domain: a set of design elements that share a power supply. Power domain is also used to denote the power supply itself.

Power state table: a table that describes the transitions between power domains. Transitions are annotated with logical expressions under which they are triggered.

Retention flop: an always-on flop that shadows the state of a flop. It retains its logic state even when the primary power supply to the cell is shut off. It is used to restore the state of a device when it is powered back up.

Level shifter: cell used to allow a signal to pass from one power domain to another.

Isolation Cell: cell used to isolate a device element from its neighbors when it is powered down.

Clock gating: power-saving technique that consists of blocking the clock signal leading to flops so that flops cannot change their state. Since their states are fixed, the downstream logic will not toggle, which saves dynamic power.

Power gating: power-saving technique that consists of shutting down the power supply to a device component, so that its power consumption is zero.

Multiple Vt: multiple voltage threshold cells. A cell speed depends on its voltage threshold. The lower its voltage threshold, the faster the cell is, but the higher its leakage power. High Vt cells are used for non-timing critical parts of the circuit, while low Vt cells are used for critical paths only, so that the overall leakage power is reduced.

Multiple voltages, Voltage islands, MVDD: a component of a circuit can operate under several voltages, or components can have different operational voltage. The higher the voltage, the faster the component is, the higher its leakage and dynamic power.

Dynamic power: the power dissipated by a circuit due to its cells switching from one state to the next. It is proportional to Vdd²tr, where Vdd is the voltage supply of the cell, and tr is its transition rate (or toggle rate) per second.

Leakage power, static power: the power dissipated due to the leakage current passing through transistors. Practically it is the power dissipated when the cell does not toggle. It is proportional to Vdd exp(- Vt / T), where Vdd is the voltage supply of the cell, Vt is its voltage threshold, and T the temperature.

Related posts:

1. Automated low-power design flow is up for grabs (Part II)
2. Can Tabula and Tier Logic be successful?
3. Is FPGA a sustainable market for EDA?