Archives
August 27th, 2011 | Tags: EDA, low power, synthesis, verification | Category: EDA

Mentor quitting on ESL?

So you got the news: Calypto acquired Catapult-C, the ESL synthesis tool from Mentor Graphics. Calypto has been into low power (using notably sequential optimization techniques) and sequential verification for a while. And the company has always been very close to Mentor Graphics: it had integrated its verification tool with Catapult-C as early as 2005. [...] [...]

Continue reading Mentor quitting on ESL?

August 27th, 2011 | Tags: EDA, low power, synthesis, verification | Category: EDA | 2 comments
June 11th, 2010 | Tags: EDA, FPGA, synthesis, Xilinx | Category: EDA, FPGA

Who should worry about Xilinx and Oasys partnership?

Xilinx announced that it signed a multi-year strategic licensing agreement to use Oasys’ synthesis. What does that mean for the FPGA and EDA community? Oasys’ product, RealTime Designer, is claimed to be 10x-60x faster than the competition. Among other things, it uses AIG-based optimization. This technology is best illustrated by UC Berkeley’s ABC synthesis: several [...] [...]

Continue reading Who should worry about Xilinx and Oasys partnership?

June 11th, 2010 | Tags: EDA, FPGA, synthesis, Xilinx | Category: EDA, FPGA | 7 comments
April 20th, 2010 | Tags: EDA, FPGA, synthesis, verification | Category: EDA, FPGA

Is FPGA a sustainable market for EDA?

A FPGA company makes revenue with the hardware: it sells its device, and gives away its design tools –synthesis, place-and-route. Yet the EDA industry has had success with its own (non-free) FPGA synthesis solutions. For good reasons: in its days, Synplicity’s Synplify was the best FPGA synthesis out there. Synopsys acquired Synplicity two years ago, [...] [...]

Continue reading Is FPGA a sustainable market for EDA?

April 20th, 2010 | Tags: EDA, FPGA, synthesis, verification | Category: EDA, FPGA | 11 comments
October 6th, 2009 | Tags: ASIC, EDA, low power, power gating, synthesis, verification | Category: EDA

Automated low-power design flow is up for grabs (Part II)

A previous post showed a very-high level view of low power design with UPF/CPF. Power gating, a must-do for mobile products, is still a very manual process, and verifying the correctness of its implementation is a very challenging task. In this follow-up post, I single out some aspects of the power-gating flow, and I hint [...] [...]

Continue reading Automated low-power design flow is up for grabs (Part II)

October 6th, 2009 | Tags: ASIC, EDA, low power, power gating, synthesis, verification | Category: EDA | 2 comments
October 5th, 2009 | Tags: ASIC, EDA, low power, power gating, synthesis, verification | Category: EDA

Automated low-power design flow is up for grabs (Part I)

Low power is becoming more and more critical as the number of mobile and wireless applications is increasing. Battery life is a feature that can make the difference between a success and a flop. Remember the first version of the iPhone? All praised the touch screen interface, but so many criticized its poor battery life. [...] [...]

Continue reading Automated low-power design flow is up for grabs (Part I)

October 5th, 2009 | Tags: ASIC, EDA, low power, power gating, synthesis, verification | Category: EDA | Leave a comment