Olivier Coudert on August 27th, 2011

So you got the news: Calypto acquired Catapult-C, the ESL synthesis tool from Mentor Graphics. Calypto has been into low power (using notably sequential optimization techniques) and sequential verification for a while. And the company has always been very close to Mentor Graphics: it had integrated its verification tool with Catapult-C as early as 2005. […]

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Olivier Coudert on June 11th, 2010

Xilinx announced that it signed a multi-year strategic licensing agreement to use Oasys’ synthesis. What does that mean for the FPGA and EDA community? Oasys’ product, RealTime Designer, is claimed to be 10x-60x faster than the competition. Among other things, it uses AIG-based optimization. This technology is best illustrated by UC Berkeley’s ABC synthesis: several […]

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Olivier Coudert on April 20th, 2010

A FPGA company makes revenue with the hardware: it sells its device, and gives away its design tools –synthesis, place-and-route. Yet the EDA industry has had success with its own (non-free) FPGA synthesis solutions. For good reasons: in its days, Synplicity’s Synplify was the best FPGA synthesis out there. Synopsys acquired Synplicity two years ago, […]

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Olivier Coudert on October 6th, 2009

A previous post showed a very-high level view of low power design with UPF/CPF. Power gating, a must-do for mobile products, is still a very manual process, and verifying the correctness of its implementation is a very challenging task. In this follow-up post, I single out some aspects of the power-gating flow, and I hint […]

Continue reading about Automated low-power design flow is up for grabs (Part II)

Olivier Coudert on October 5th, 2009

Low power is becoming more and more critical as the number of mobile and wireless applications is increasing. Battery life is a feature that can make the difference between a success and a flop. Remember the first version of the iPhone? All praised the touch screen interface, but so many criticized its poor battery life. […]

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