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Xilinx announced that it signed a multi-year strategic licensing agreement to use Oasys’ synthesis. What does that mean for the FPGA and EDA community? Oasys’ product, RealTime Designer, is claimed to be 10x-60x faster than the competition. Among other things, it uses AIG-based optimization. This technology [...] Continue reading Who should worry about Xilinx and Oasys partnership? A FPGA company makes revenue with the hardware: it sells its device, and gives away its design tools –synthesis, place-and-route. Yet the EDA industry has had success with its own (non-free) FPGA synthesis solutions. For good reasons: in its days, Synplicity’s Synplify was the best FPGA synthesis out there. Synopsys acquired Synplicity [...] Continue reading Is FPGA a sustainable market for EDA? October 6th, 2009 | Tags: ASIC, EDA, low power, power gating, synthesis, verification | Category: EDA
A previous post showed a very-high level view of low power design with UPF/CPF. Power gating, a must-do for mobile products, is still a very manual process, and verifying the correctness of its implementation is a very challenging task. In this follow-up post, I single out some aspects of the power-gating flow, and [...] Continue reading Automated low-power design flow is up for grabs (Part II) October 5th, 2009 | Tags: ASIC, EDA, low power, power gating, synthesis, verification | Category: EDA
Low power is becoming more and more critical as the number of mobile and wireless applications is increasing. Battery life is a feature that can make the difference between a success and a flop. Remember the first version of the iPhone? All praised the touch screen interface, but so many criticized its poor [...] Continue reading Automated low-power design flow is up for grabs (Part I) |
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