However FPGA-based prototyping is impaired by a complex setup, and its limited debugging capabilities leads to iterate costly place-and-route runs. The setup phase, or “bring-up” phase, partitions and maps the SoC into a multi-FPGA board. This is a complicated process, and verifying that the RTL has been properly mapped into the board is no small feat. Once that verification is done, system-level debugging can begin. A faulty behavior must first be identified as a software or hardware issue. Since the software and hardware debugging tools are disjointed, identifying the actual source of a problem a tedious task. Debugging the RTL is time consuming because a traditional FPGA prototype environment offers no visibility in the FPGA, and every time an ECO is applied, place-and-route must be run again.

InPA Systems proposes to address some of these limitations. The company claims that today’s trial-and-error debugging method can be significantly improved upon when software and hardware debuggers are synchronized with InPA’s “active debug” method, which can easier identify the source of issues at run time. The lack of visibility into the FPGA as well as a loose cross-reference between RTL code and multiple FPGAs makes debugging very complicated. InPA promises “full visibility” of signals, allowing users to capture complex scenarios when running the design at speed, so that they can analyze system faults more thoroughly and easily.

Reading more in depth, this how I understand what InPA is proposing:

• Integrate the RTL simulation and FPGA prototype environments to automatically verify that the mapping of the RTL into the multi-FPGA board is correct. This reduces substantially the cost of the “bring up” phase, which is usually done with a much slower gate-level simulation.
• Integrate the software and hardware debug environments so that engineers can catch issues easier when integrating both software and hardware in the FPGA prototype environment.
• Current prototype methods can capture the signals associated with a faulty condition, but they cannot do this over multiple FPGAs. Isolating a hardware problem in a RTL code that has been mapped into multiple FPGAs is then extremely complicated. InPA uses the same integrated environment to bring the user with full visibility of the signals, as well as cross-link of the RTL, across multiple FPGA. This helps identify the origin of faults in a much efficient manner.

The figure below shows how InPA showcases its “Active Debug” and “Full Visibility” technology. It uses hardware and software to enable full visibility into the FPGA design. It integrates the custom or off-the-shelf FPGA prototype environment (FPGA netlist and circuit board) with the simulator environment so that the user can see inside the design during verification. The Embedded Vector Processor Interface (EVPI) is inserted along with the Design Under Verification (DUV) into the FPGA to facilitate the communication between the simulator and the DUV. The debugging interface captures stimulus and response vectors for regression tests and debugging. InPA provides a close control of the debugging process by giving users an extensive triggering capabilities with its Embedded Micro Machines (EMMs), which can capture faulty conditions over multiple FPGAs and make signals fully visible –no FPGA recompilation required. I must admit that this part is bit obscure –does that mean that all RTL signal are preserved upfront, or that enough signal redundancy is kept to reconstruct any internal signal?

InPA Systems was founded in October 2007 by two emulation and verification EDA veterans, Thomas Huang, CTO, and Michael Chang, CEO. Notable in InPA’s business model is that the company offers an open system, supporting all popular fixed “off-the-shelf” prototype systems as well as custom prototype systems. The company expects to start beta testing with a few close prospects in late Q3’10, and to make its first product available in Q4’10. No doubt we will hear more from this company in the next few months.

Related posts:

1. Why FPGA startups keep failing
2. Is FPGA a sustainable market for EDA?
3. Plunify, a glimpse at EDA in the cloud

Instead, I have chosen to share my absolutely non-exhaustive, completely biased view of DAC. I will then publish a couple of posts focused on specific themes in the next few days.

Attendance

The 47^th DAC was held June 13-18 at the Anaheim Convention Center in California. The preliminary attendance numbers are reported as follow:

• Total full conference: 1554
• Total exhibit attendees: 3444 (24% international)
• Exhibitors, visitors, and guests: 2557
• Total attendees: 6001

The final attendance numbers are usually a few percent higher.

For a fair comparison, I pulled out the preliminary attendance numbers of the past conferences. I was first fooled by the way the numbers were labeled this year –see the comments below, and a big thanks to Sean to bring me the correct interpretation. The table below shows the correct data, excluding booth staff. It shows a sharp decline (33%) of the total attendance compared to last year in San Francisco. Not having DAC in San Francisco means higher cost for most of the attendees –many of them are from the Silicon Valley–, which is clearly reflected in the attendance numbers.  But if we compare this year’s numbers with the 2008 DAC venue held at the same location, we see the same sharp decline (28%). Note the drop in exhibits-only attendees (-41% w.r.t. 2009, -21% w.r.t. 2008), not a good sign as this number captures most of the customer audience.

DAC preliminary attendance numbers (not including booth staff)

This year’s DAC comes after one of the worst recession, but looking forward to a very strong semiconductor growth in 2010 and 2011, which should eventually translate into a mildly better business for EDA. The exhibition was well attended on Monday, with a sharp decline on Wednesday –lots of people left by that time.

The buzz

With Cadence’s EDA360 campaign in the background, and the fresh acquisitions of Denali by Cadence and Virage Logic by Synopsys, it felt that IP was the buzzword of the day. IP design here, IP verification there, verification IP everywhere, the overall SoC design looked like an IP integration problem that EDA was gearing up to take on. Embedded software and ESL were also showcased by Cadence and Mentor Graphics as part of their SoC focus.

Verification

There was a booth dedicated to UVM/OVM (Universal Verification Methodology/Open Verification Methodology). These methodologies offer open and interoperable verification solutions. They both support multiple languages and simulators, and enable verification IP, so critical to SoC design. The message was well received and had a strong attendance.

Still on the verification side, new products and startups are trying to repeat the success of Certess (acquired by SpringSoft last year). Advanced formal verification tools (e.g., property checkers) are slow to find acceptance by the design community. Instead these new products and startups leverage the existing test bench and simulation methodology in place to produce better coverage or faster simulation. Notably missing in this space was NuSym, a no-show at this year’s DAC, confirming the rumors that the startup that demonstrated “intelligent” simulation two years ago is actively looking for a buyer.

The whole simulation and emulation space was strong. Mentor’s Veloce is showing impressive numbers, and is ready to take on Cadence’s Palladium. Eve will likely take notice, and this may bring it closer to Synopsys.

Magma’s Tekton offers sign-off quality multi-mode/multi-corner static timing analysis for multi-million gate circuits. The tool has been designed from the ground up, and tailored for multi-threading and distributed systems. It is a clear competitor to Synopsys’ PrimeTime, even though running PrimeTime *is* the signoff for most customers.

Design and implementation

On the P&R and backend side, nothing really stood out. Synopsys clearly gained in QoR, Mentor’s momentum with Sierra’s Olympus is still strong, and Magma keeps lagging behind, especially in runtime. Atoptech and Azuro, although showing pretty good numbers (verified at customers’), are still considered more like add-ons that comprehensive solutions. This segment looks more and more commoditized, and only the high-end (20nm and below) and 3D seem to offer new growth opportunities in that space.

Oasys, the darling of last year’s DAC, did not make as much as a splash this time, despite its recent announcement with Juniper Networks and Xilinx. Nobody question the speed and capacity of their tool, as well as the clock cycle it can achieve. But some raised concerns regarding the area of their netlists for ASIC.

On the fringe

This is the “stuff I liked that may be too small to be noticed”, even more so since two of these three companies didn’t have a booth at DAC…

Low power is still under-represented, even though power gets worse with smaller geometries, and power management remains mostly a very manual process. In that space I liked Docea Power, which can simulate system-level models to analyze power consumptions and thermal behaviors. System-level analysis can bring the biggest power savings. It also has a significant impact on the packaging, which is still a domain where conservative approaches are preferred to more cost-efficient, but riskier, choices.

A comprehensive system-level design framework is really an IDE (Integrated Development Environment) for SoC, where hardware and software can be designed together, written and simulated together, and where the HW/SW tradeoffs can easily be explored. IDEs have been used in software for a long time, but are a novelty to hardware designers. Sigasi proposes an IDE for VHDL –what Microsoft’s Visual Studio is to C++. Although this is still light-years away from a SoC IDE, this is a hint into the future of writing RTL.

We heard several claims that cloud computing is coming to EDA (or the converse?). Xuropa best illustrates that (slow) move. They provide turn-key online community solutions for the electronic design industry. Their main customers, Cadence and Synopsys, are using the services for CRM and virtual demo only. But Xuropa could become a platform that enables collaborative design in the cloud, providing secured access to a multi-vendor flows. More on this in a future post.

Last words

I felt that there was a lot of system-centric messages (best captured by EDA360), and attempts at rising the abstraction level for higher productivity. EDA vendors are forced to see the big picture –full system design, software and hardware together. But as pointed out by Steve Jones (TI) at Cadence’s Silicon Realization Luncheon, EDA is still missing out on two important parts of the SoC design. One is that customers want a first-silicon that is functionally operational, and Steve singled out the need for useable verification IP –UVM/OVM is a step in the right direction. The other is analog –mixed-signal design is the rule, and there is no good integration there.

No related posts.

EDA360, John Bruggeman’s brainchild, is a manifesto that promotes a vision for the future of EDA. In a nutshell, it states the following:

• So far EDA has been providing the tools to IC creators: design, implement, and verify ICs.
• With the development cost of 32nm SoC reaching $100M, only a handful of semiconductor companies will still create ICs in the next future.
• With modern consumer electronics fueled by apps-based model, electronic design is moving from a hardware-first to a software-centric industry.
• Future SoC will be designed top-down, with software and apps requirements driving the integrations of IPs, DSPs, GPUs, CPUs and cores (ARM, MIPS, x86, etc).
• EDA needs to provide the environment for integrating and optimizing software and hardware resources.

One can disagree with some figures of EDA360’s white paper (e.g., today’s cost of SoC software, placed at 50% of the total SoC development cost, which looks overstated). One can argue that this document states the obvious –that consumer electronics are differentiating with the end applications, which is more and more software dependent, which means EDA needs to focus more on the software aspect if it wants to stay relevant.

But that would not give justice to this document. EDA360 is a detailed, well articulated, and viable vision of what EDA should be. It is a call for action that can revitalize an industry that has been looking for new areas of growth.

EDA’s main value proposition must follow its customers’ evolution. Semiconductor companies are moving from silicon to system companies, which provide application-ready hardware/software platforms, targeted for a precise market within a narrow time-to-market window.

The best example is the evolution of mobile phones. It started with heterogeneous HW/OS/SW devices, all proprietary and hardware centric. Then the iPhone came in 2007, providing a HW+OS environment with a SDK (Software Development Kit) for developers in 2008, together with the App Store and its 70/30 seller/store profit sharing model. As for May 2010, the App Store offers 200,000+ apps and received over 4B downloads, and it produced a Q1’10 revenue for Apple estimated at $150-225M. The next step was Google that released Android OS for mobile devices as open source in 2008. As for May 2010, there are 17 manufacturers proposing mobile phones built on the Android platform, and 12 offerings for tablets and e-readers. The semiconductor companies providing the hardware are really delivering complete Android-enabled, apps-ready, HW/SW systems.

So where does that leave EDA? EDA already started to address some of the issues. HW/SW simulation, virtual prototyping, IP reuse, verification IP, and ESL/C-flavor synthesis have received significant investments by Cadence, Mentor, and Synopsys. Synopsys acquisition of Vast (virtual prototyping) and CoWare (ESL) was not as noticeable as Cadence’s acquisition of Denali, but it participates of the same logic. Cadence’s Open Integration Platform was announced early May, and intends to grow an ecosystem that will help realizing EDA360.

Still, we are far from an integrated development environment (IDE) for SoC, which would meet EDA360’s vision. For instance, IP reuse is still elusive –the cost of IP integration is often comparable to the cost of developing a new IP.

I don’t know whether EDA will meet the challenge of an environment where the software application drives the cores selection and power management, where IPs are selected according to some cost/performance tradeoffs, where the different hardware components are integrated seamlessly, and where the verification of the software together with the hardware is done incrementally. I don’t know whether this will result in moving from a $5B to a $25B industry. But I applaud a strong vision that gives a new roadmap for the future of EDA. It will certainly impact the industry. Already we see some EDA vendors espousing EDA360’s message, like Duolog, and Cadence’s acquisition of Denali shows it is serious about fulfilling the vision. Also if the SoC’s silicon results mostly from integrating IPs and cores, RTL synthesis and place & route will be commoditized. Only vendors able to provide HW/SW integration and verification will emerge as the next leaders.

No related posts.

After about a year of seeing a desolated EDA landscape, littered with startups that could not find the money to survive to the next decade, or with promises that faltered as the semiconductor industry was hit hard with inventories it could not clear, the beginning of 2010 is suddenly looking brighter. Well, not as bright as I would like it to be, but there is definitely a sense of revival.

The semiconductor industry is announcing better-than-expected numbers for CY09Q4, and the recent Consumer Electronic Show (CES) led new expectations for exciting products that should be available within the year. How will this impact EDA? If impact there is, it will not be immediate, as many of its customers are still holding on their investments for the rest of the year, since most of their designs can be done with their current flows and tools. But, as pointed out by Richard Goering, CES showcased the hot products to come, and some will definitely require EDA tools to step up. Whether it is tablet PCs, ever more powerful mobile phones, 3D-TVs (over-hyped, if I may say so), USB 3.0, or wifi-enabled cars, there are plenty of avenues where mixed signals, low power, packaging, and high-capacity SoC design and verification tools can shine.

These are all familiar topics, but CES stressed the need for better, automated, and scalable solutions.

• Mixed signals will help Cadence –Synopsys does not have a credible solution there, and Magma is still too young in this market to push its Titan offering, regardless of its technical merits.
• Low power will be a leveled field, because there is no one-vendor comprehensive solution covering all its many facets; e.g., CPF/UPF support (Cadence and Synospys-Mentor-Magma respectively); RTL-level low power synthesis, which requires complex IP or/and manual architecturing; power-efficient clock tree synthesis, best done by Azuro and Mentor’s Olympus; and last but not least, low power verification, still led by Cadence’s Conformal.
• Early packaging estimation will be an interesting challenge –table PC and mobile phones require very thin, heat-dissipating, robust devices. Mentor and Cadence should capitalize on some of their technology and experience there.
• Large SoC design and verification is becoming more acute. Synospys and Mentor look positioned to make a move against an aging First Encounter-based Cadence solution.

It is still difficult to find money to finance new ventures or keep existing startups alive, so predicting what will come from startups is quite difficult for 2010. We will surely see whether Oasys, with its promise of 10-50x larger and faster synthesis, are for real. We will see whether ATopTech can separate itself from the increasingly commodity-like backend offering. We may see whether ESL or some flavor of C/C++-based hardware design environment can help addressing SoC challenges –for designing and verifying both the silicon and the software.

There is a window of opportunities driven by a recovering consumer electronic market, where EDA can demonstrate that innovation and responsiveness to the next technological challenge does pay off. Let the game begin.

No related posts.