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October 6th, 2009 | Tags: ASIC, EDA, low power, power gating, synthesis, verification | Category: EDA

Automated low-power design flow is up for grabs (Part II)

A previous post showed a very-high level view of low power design with UPF/CPF. Power gating, a must-do for mobile products, is still a very manual process, and verifying the correctness of its implementation is a very challenging task. In this follow-up post, I single out some aspects of the power-gating flow, and [...]

Continue reading Automated low-power design flow is up for grabs (Part II)

October 6th, 2009 | Tags: ASIC, EDA, low power, power gating, synthesis, verification | Category: EDA | 2 comments
October 5th, 2009 | Tags: ASIC, EDA, low power, power gating, synthesis, verification | Category: EDA

Automated low-power design flow is up for grabs (Part I)

Low power is becoming more and more critical as the number of mobile and wireless applications is increasing. Battery life is a feature that can make the difference between a success and a flop. Remember the first version of the iPhone? All praised the touch screen interface, but so many criticized its poor [...]

Continue reading Automated low-power design flow is up for grabs (Part I)

October 5th, 2009 | Tags: ASIC, EDA, low power, power gating, synthesis, verification | Category: EDA | Leave a comment