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No doubt that for the next two weeks you will find many DAC reports in blogs and corporate marketing websites. So I tried not to write yet another DAC report, with a long list of companies and products. Instead, I have chosen to share my absolutely non-exhaustive, completely biased view of DAC. I will then publish [...] Continue reading DAC 47th digest: what you missed (even if you were there) Yes, did you feel it? No, I am not talking about the two earthquakes that I felt last week in San Jose, shaking the buildings, and leaving people with that weird feeling that they just experienced a whisper of the Big One to come. No, I am talking about the tremor in [...] Continue reading Did you feel the tremor? The 2010 challenges for EDA October 6th, 2009 | Tags: ASIC, EDA, low power, power gating, synthesis, verification | Category: EDA
A previous post showed a very-high level view of low power design with UPF/CPF. Power gating, a must-do for mobile products, is still a very manual process, and verifying the correctness of its implementation is a very challenging task. In this follow-up post, I single out some aspects of the power-gating flow, and [...] Continue reading Automated low-power design flow is up for grabs (Part II) October 5th, 2009 | Tags: ASIC, EDA, low power, power gating, synthesis, verification | Category: EDA
Low power is becoming more and more critical as the number of mobile and wireless applications is increasing. Battery life is a feature that can make the difference between a success and a flop. Remember the first version of the iPhone? All praised the touch screen interface, but so many criticized its poor [...] Continue reading Automated low-power design flow is up for grabs (Part I) |
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