Four months after that post, Tier Logic ceased to exist after failing to close its second round of funding.

On March 28^th 2011, Tabula announced it has secured $108 million in Series D funding. Crosslink Capital and DAG Ventures are the main investors, with Balderton Capital, Benchmark Capital, Greylock Partners, Integral Capital, and New Enterprise Associates renewing their confidence in that fourth round. This brings the total investment in Tabula to $214 million, not a small feat, given that the semiconductor industry has found difficult to entice VC money for years.

Also Tabula said that Cisco was a customer, and that a Tier 1 equipment vendor has completed a base station design using Cisco’s chips.

So with $108 million in hands, Cisco as a customer, Tabula’s future looks bright, right?

I still want to see how the software part will unroll. Tabula announced Stylus back in February, which provides a full synthesis and P&R that automatically manages the reconfiguration and mapping to the device. Not to deny any innovation, Stylus is running in the cloud and can be used from a web browser. I am looking forward to hearing customer feedback of the experience.

Tabula has certainly the means to hire top-notch engineers to produce the best possible synthesis and P&R, attract the best sales people, and possibly roll out new hardware. Tabula claims they can provide the same capacity and performance offered by a $1000 leading FPGA (read, Xilinx or Altera) for only $200. And, in the words of their VP marketing, they are looking at “not just the $5 billion FPGA market but the $110 billion market made up of FPGAs, ASSPs and ASICs”.

I will wait and see with a healthy skepticism, given the many promises and still-to-be-seen achievements of the virtual 3D technology.

No related posts.

Plunify’s motto is to simplify the FPGA design process. The founders’ claim is that there are too many, somewhat disjointed steps, to produce an operational FPGA: synthesis, IPs, place-and-route, testing, debugging, many steps which yield much iteration before reaching the desired performance trade-off. That is not including the hassle to install and maintain the software, as well as the hardware resources. Last but not least, it is difficult to compare performances for multiple devices across multiple FPGA vendors –and device price should eventually be part of the trade-off picture.

Plunify aims at making FPGA design as simple as possible. Its use of Amazon’s cloud infrastructure results in a platform that abstracts unnecessary details away from users. Using the cloud also significantly speed up synthesis and place-and-route for multiple trade-offs. Plunify’s current beta platform supports Altera and Xilinx, as well as two open source simulators, Icarus Verilog and GHDL.

Plunify is currently offering three different packages: Walk, Run, and Fly. Each package includes 750 hours in the cloud (this is one full CPU time month), with full access to Xilinx and Altera devices and IPs. CPU speed, RAM and disk space increases with the level of the package, starting at 1.7Gb RAM and 1Gb disk space with “Walk”. Although pricing is not fully frozen, the base “Walk” package should be available for around $350 USD. Given the service it provides, this is a very compelling value.

Plunify is currently working on new features. One consists in allowing the user to input a range of timing constraints to let Plunify’s cloud-based platform explore these optimization scenarios in parallel, which will come up with optimum solutions in a fraction of the time an iterative flow would take. Another is to enable online collaboration and version control for round-the-clock, distributed design teams.

Granted, automatically exploring a range of timing constraints in parallel is not totally new. Both Xilinx and Altera, as well as some EDA vendors, have works in progress in that area. But Plunify pushes automation and ease-of-use way further: on-line, vendor agnostic, diligent performance tradeoffs delivery. When it comes to being in the cloud, security is design houses’ top concern. Plunify uses SSL for all communication to its website, and it uses the proven and pretty much de-facto standard Amazon S3 for storage. Still I anticipate that security will be one of the major hurdle to Plunify’s success. The next year will show how Plunify is received by the FPGA design community. Personally, I like to think that Plunify is a hint at the future of EDA: online, streamlined, and in the cloud. And of course, a totally different business model.

Related posts:

1. Cloud computing: an opportunity for EDA
2. EDA in the cloud: shall we be scared?
3. Synopsys is getting into the cloud

However FPGA-based prototyping is impaired by a complex setup, and its limited debugging capabilities leads to iterate costly place-and-route runs. The setup phase, or “bring-up” phase, partitions and maps the SoC into a multi-FPGA board. This is a complicated process, and verifying that the RTL has been properly mapped into the board is no small feat. Once that verification is done, system-level debugging can begin. A faulty behavior must first be identified as a software or hardware issue. Since the software and hardware debugging tools are disjointed, identifying the actual source of a problem a tedious task. Debugging the RTL is time consuming because a traditional FPGA prototype environment offers no visibility in the FPGA, and every time an ECO is applied, place-and-route must be run again.

InPA Systems proposes to address some of these limitations. The company claims that today’s trial-and-error debugging method can be significantly improved upon when software and hardware debuggers are synchronized with InPA’s “active debug” method, which can easier identify the source of issues at run time. The lack of visibility into the FPGA as well as a loose cross-reference between RTL code and multiple FPGAs makes debugging very complicated. InPA promises “full visibility” of signals, allowing users to capture complex scenarios when running the design at speed, so that they can analyze system faults more thoroughly and easily.

Reading more in depth, this how I understand what InPA is proposing:

• Integrate the RTL simulation and FPGA prototype environments to automatically verify that the mapping of the RTL into the multi-FPGA board is correct. This reduces substantially the cost of the “bring up” phase, which is usually done with a much slower gate-level simulation.
• Integrate the software and hardware debug environments so that engineers can catch issues easier when integrating both software and hardware in the FPGA prototype environment.
• Current prototype methods can capture the signals associated with a faulty condition, but they cannot do this over multiple FPGAs. Isolating a hardware problem in a RTL code that has been mapped into multiple FPGAs is then extremely complicated. InPA uses the same integrated environment to bring the user with full visibility of the signals, as well as cross-link of the RTL, across multiple FPGA. This helps identify the origin of faults in a much efficient manner.

The figure below shows how InPA showcases its “Active Debug” and “Full Visibility” technology. It uses hardware and software to enable full visibility into the FPGA design. It integrates the custom or off-the-shelf FPGA prototype environment (FPGA netlist and circuit board) with the simulator environment so that the user can see inside the design during verification. The Embedded Vector Processor Interface (EVPI) is inserted along with the Design Under Verification (DUV) into the FPGA to facilitate the communication between the simulator and the DUV. The debugging interface captures stimulus and response vectors for regression tests and debugging. InPA provides a close control of the debugging process by giving users an extensive triggering capabilities with its Embedded Micro Machines (EMMs), which can capture faulty conditions over multiple FPGAs and make signals fully visible –no FPGA recompilation required. I must admit that this part is bit obscure –does that mean that all RTL signal are preserved upfront, or that enough signal redundancy is kept to reconstruct any internal signal?

InPA Systems was founded in October 2007 by two emulation and verification EDA veterans, Thomas Huang, CTO, and Michael Chang, CEO. Notable in InPA’s business model is that the company offers an open system, supporting all popular fixed “off-the-shelf” prototype systems as well as custom prototype systems. The company expects to start beta testing with a few close prospects in late Q3’10, and to make its first product available in Q4’10. No doubt we will hear more from this company in the next few months.

Related posts:

1. Why FPGA startups keep failing
2. Is FPGA a sustainable market for EDA?
3. Plunify, a glimpse at EDA in the cloud

Tier Logic had a unique value proposition: you could turn its FPGA into an ASIC in a predictable time and cost. It had a working silicon and a proven production tool, and achieved to do so with spending only $20M.

It is a pity to see that a company with such a good technology and such an attracting business proposition must shut down because of lack of interest from VCs. You have to wonder which strings you have to pull in the investment community to get the attention you deserve.

Although Tier Logic will likely attempt to sell its technology to a Xilinx or an Altera, it is also quite likely that whoever the buyer is will simply buy Tier Logic’s patents to bury them. Too bad.

After Abound Logic‘s shut down 6 weeks ago, another startup showing how hard it is to be successful in FPGA.

Related posts:

1. Can Tabula and Tier Logic be successful?
2. RIP Abound Logic

Oasys’ product, RealTime Designer, is claimed to be 10x-60x faster than the competition. Among other things, it uses AIG-based optimization. This technology is best illustrated by UC Berkeley’s ABC synthesis: several FPGA startups reported that ABC boosted significantly the speed, capacity, and quality of their synthesis engines. No question that Oasys’ synthesis is competitive, at least in the FPGA world.

Xilinx is an investor into Oasys, and it has been toying with their synthesis technology for at least a year, so it’s not like they just discover each other. Xilinx has to close a software technological gap with respect to its closest competitor, Altera, and a fast, high capacity synthesis will certainly help.

Synthesis speed is key here. Until recently FPGA design was mostly an iterative process: synthesize, simulate, and debug (i.e., change in the RTL) until the performances and functionality of the design were satisfactory. That trial-and-error approach becomes impractical as the size of FPGA devices is increasing to the point that one single iteration takes hours, if not a day. Having a 10x speedup in synthesis means you can restore that familiar design iteration for a few more years.

Verification has become a bottleneck in FPGA. Simulating is used and will still be used in the future. But FPGA’s complexity requires a more complete verification methodology, like formal verification. However formal verification has trouble addressing optimization techniques heavily used in FPGA synthesis, like retiming and state re-encoding. An ABC-like optimization engine comes with a built-in formal verifier that can check independently the correctness of every incremental optimization steps performed during the optimization run. The correctness of the resulting netlist comes with a very high degree of confidence, and only the RTL description needs to be simulated.

Xilinx’ customers will benefit from that technology, and catch up with Altera’s synthesis. As for the EDA vendors selling their own FPGA synthesis, they all use or will use some flavor of AIG-based optimization. Differentiation will be done on the smartness of the high-level optimization –datapath, IPs–, the user experience (GUI), the integrated verification environment (still to be demonstrated), and of course the bottom-line: QoR –clock cycle, area, and power. The race is on.

Related posts:

1. What to read in Xilinx’ and Altera’s third quarter results
2. How can Xilinx improve its bottom line
3. Is FPGA a sustainable market for EDA?

Abound logic, previously known as M2000, was founded by three EDA veterans who had previously started Meta Systems. Meta Systems developed the industry’s first emulation system based on custom FPGAs, which was to become the basis for the Abound Logic device after Meta Systems was acquired by Mentor Graphics in May 1996.

Abound logic’s device, the Raptor FPGA, offered in 65nm technology the capacity of 774k CLBs, each containing a 4-input LUT. This made the Raptor the largest FPGA on the market at a time.

Abound logic was in discussions to close another financing round, estimated around $20M, but one of the main tentatively new investor pulled out, which put to rest the last investment opportunities.

Related posts:

1. RIP Tier Logic
2. Can Tabula and Tier Logic be successful?

In a world where FPGA software design is expected to be free (or very cheap, compared to it ASIC counterpart), is there still a market for EDA companies to sell their FPGA solutions? Synplicity stopped growing after it built its success on FPGA synthesis. Is that the fate of EDA for FPGA?

There are several forces at play here: device complexity, software complexity, and know-how.

The complexity of FPGA starts to rival that of ASIC’s. The largest FPGA devices contain 100,000’s of LUTs and registers, 1000’s of DSP components, and are equivalent to 1+ million gate designs. The increasing device size requires faster synthesis and larger capacity. It also strains verification because simulation costs are augmenting accordingly. The days were a designer could complete her FPGA project with a simple write-RTL/synthesize/simulate/fix iterative flow are gone.

FPGA companies differentiate with their devices’ speed, capacity, and power consumption. But beyond the raw hardware features, software to design FPGA has become a key for success. Altera learnt the lesson the hard way 10 years ago when it released software that was not ready: Altera quickly lost its top customers to Xilinx, while it could have become the undisputed #1 FPGA vendor. Some FPGA startups in the past could not get off the ground because they fail to deliver good synthesis for their device. Closer to us, we have heard about Tabula’s chronic problems to bring up its synthesis before it finally announced its device earlier this year. And Abound Logic’s huge netlist has stretched the capacity of today’s FPGA synthesis.

Altera has now a software powerhouse, and is meticulous about its software design and testing. Xilinx is currently going through a major overhaul of its software to catch up with its main competitor. There is no question that software is taken very seriously by the two vendors –they both have a couple hundreds engineers dedicated to provide customers with a full design tool suite.

So does EDA has any future in FPGA synthesis? There will always be FPGA startups looking for an OEM with Synopsys and Mentor, but this is not enough. The EDA industry must showcase a comprehensive FPGA development environment that will cover design, synthesis, and verification:

• Verification is becoming ever more costly for FPGAs, as it already is for ASICs. Formal verification for FPGA is still embryonic –FPGA synthesis uses retiming and FSM re-encoding that makes formal verification quite difficult.
• Synthesis of complex systems with a large IP spectrum is an area of expertise that EDA must leverage. Also EDA could provide a much-needed improvement in power management.
• As for design, EDA must seize on the FPGA community’s ability to adopt new methodologies much faster than the ASIC community. ESL, SystemC, and C/C++ as hardware description languages are the right direction.

If EDA wants to compete with the few hundred software engineers of Xilinx and Altera, it needs to deliver a best-in-class and innovative FPGA design environment. Else it will end up as a no-growth by-product of ASIC synthesis.

Related posts:

1. Meet InPA, a newcomer in FPGA-based prototyping
2. The formal verification market is still untapped
3. Why FPGA startups keep failing

The dominant factor in classical FPGA architecture is the interconnect: most of the die area is taken by the wires and the interconnect switches and muxes. If you can somehow reduce the area dedicated to interconnect, you can augment the logic density and lessen the cost of the device. Tabula and Tier Logic pitch a 3D architecture to address the interconnect bottleneck, albeit in very different flavors.

Tabula innovative design is based on its ability to reconfigure itself, up to 8 times with a clock running at 1.6GHz. At each cycle a cell can change its functionality, its latch configuration, and its interconnect. The time-multiplexing increases the amount of logic that can be fit on the same area. It is like having 8 layers (or “folds”) of cells stacked on top of each other along a time axis, with very short connection between cells at the same (x,y) coordinate but in two adjacent folds. At each cycle one jumps to the next fold and feeds the new configured logic with the results of the previous fold. Tabula claims they increase the logic density by 2.5x compared to classical FPGA architectures.

Tier Logic’s design idea is to place the SRAM cells that configure the interconnect muxes on top of the routing layers, instead of having them distributed throughout the logic die area. Doing so leaves more room for logic cells, increasing the cell density by about 50% according to the company. The design flow will not throw anybody off: it uses Mentor’s Precision for synthesis, and is followed by Tier Logic’s mapping and P&R.

A big plus touted by Tier Logic is the ability of moving painlessly from their device to an ASIC. Simply replace the interconnect configuration SRAM cells at the top with metal, and voila, you obtain an ASIC with no change in timing. This is a simple, predictable process: it takes about 4 weeks to go from the SRAM configuration to a top-layer mask, and you do not need to go through a timing closure flow again, which means a non-recurring engineering cost of about $50k. This is a real bargain when you consider that moving from FPGA to ASIC usually requires a redesign that can take as long as 9 months.

So who of Tabula and Tier Logic is best positioned to challenge the duopoly Xilinx/Altera?

Tabula made it clear that they are aiming at the high-end of the FPGA market. There are a number of FPGA startups that targeted the same niche, and none survived. One reason is that it is easy for Xilinx and Altera to increase the size of their device, by simply moving to the next technology node. Tabula’s design is innovative and pushes the limits, but how far is too far? It is unclear whether the company can deliver the design tools to match their device’s challenges –they went through a complete reset a few years ago, replacing the whole software team. Verifying a device that can reconfigure itself 8 times in a loop may be another challenging problem. Increased density is obtained by continuous reconfiguration, which means extra power consumption: is it still an acceptable tradeoff? Last but not least, with 100+ people in the US, it is a well-known fact in the Silicon Valley that Tabula burns cash fast, and their funding of $106 millions so far is about to come short.

Tier Logic’s FPGA can reduce the cost of the device for the same density. But their compelling value proposition is really their FPGA to ASIC translation. This is what Altera’s HardCopy was supposed to be, a seamless and risk-free migration from FPGA to ASIC. For anybody that wants to design an application and then migrate to a low/medium volume ASIC production, this could be the most cost efficient solution. I do not know the inside story regarding the financial aspect, but their business proposal looks more solid.

So who do you think has a chance here? Let’s meet again in 3-4 quarters and see how the two companies are doing.

Related posts:

1. RIP Tier Logic
2. RIP Abound Logic
3. Why FPGA startups keep failing

Paul rightly emphasized three trends. The first one is well know: the continuously rising cost of IC designs, about $50M for today’s 45nm node. The second trend is that the fastest growing part of the design cost is software –more than half of the overall cost, Paul even claiming close to 2/3 of the overall cost. The third trend is an increasingly fragmented consumer market: the number of end products goes into the 10’s of billions, but these products are declined in many more different kinds, which means that most of them are shipping in smaller individual volumes.

Source: Morgan Stanley, Economy + Internet Trends, Web 2.0 Summit, San Francisco, Oct 2009.

This is bad news for EDA as we know it: the rising cost of design can no longer be justified if the number of units does not grow fast enough (a $50M chip starts to make sense only if it is produced for 250M units and more). Also EDA has been slow to climb up the food chain and proposes solutions for software design, which dominates the overall chip design cost.

Rising IC design cost and smaller number of units is the call for FPGA to growth even faster. Mobile applications require FPGA to do much better in terms of power consumption, but this is a hot topic (no pun intended) drawing a lot of attention and investment, and some competitive solution will emerge in the next few years. So EDA, which makes its bread and butter on IC design, should better re-align its growth strategy on software, embedded systems, HW/SW co-design, and verification. Else EDA will continue to shrink to only service the few that can still afford chip design.

The end product, as a SoC, is a puzzle where the designer mostly assembles existing cores and IPs, and decides of the tradeoff between the software and hardware parts, based on flexibility and cost factors.

I see two strong needs that EDA could build its growth on. One is functional validation of the whole system –software plus hardware. EDA has started to address the issue, even though it is still short of proposing a scalable and automated environment. To functional validation, I would also add functional flexibility: how much of the behavior can be upgraded thanks to the software part? The other need is a design navigator that would estimate the speed, area, power consumption, and cost of a SoC by exploring alternatives between cores (ARM, MIPS, etc), IPs, FPGA, and software.

Last but not least, the eternal question of an EDA serving a $250B semiconductor industry, but making less than $5B. The time-based license model has only served the interests of the semiconductor companies, to the expenses of R&D investment in EDA. Claiming a lack of innovation in the EDA industry is sometimes fair, but EDA should also innovate in business solutions instead of cannibalizing itself by cutting costs to only survive another quarter. The semiconductor industry needs a healthy EDA if it wants to address the system-level design challenges of the next 10 years. Unless, of course, a new player coming from the software world with the experience of scalable systems signs the death of the EDA industry as we know it.

Related posts:

1. The formal verification market is still untapped

Comparing the yearly fiscal exercises directly would be biased (Xilinx’ fiscal year end on March 31^st, and Altera’s fiscal year on Dec 31^st). Instead we can look at a quarter by quarter comparison, even though that can be too low a level. Better is to look for ttm (trailing twelve months) comparison to smooth out the local variations.

Source: Yahoo! Finance. All figures in thousands.

One can see that Altera’s operating margin is overall better. Also in their respective Q3’09 revenue reports, Xilinx expects its Q4’09 gross margin to improve to 62-63%, and Altera sees his to be 67-68%.  So a 3-4% operating margin gap will remain, which is significant.

On the other hand, Xilinx quotes 3145 full time employees, and Altera 2760. This means that a Xilinx employee brings back revenue about 26% higher than an Altera employee! So it all boils down to the question: how can Xilinx be more cost efficient?

One of the differences is the way software is developed. Altera’s software is mostly done in their technology center of Penang, Malaysia, with a very small core technology group in Toronto, Canada. Xilinx’s software team is mostly in the US, and only 5% of the team is in their R&D facilities in Hyderabad, India. A back-of-the-envelop calculation shows that if Xilinx had the same software team but with a US/India ratio 1/3-2/3, which is a healthy ratio for a company that can leverage its India facility, Xilinx would improve its operating margin by one point.

If you extend the same reasoning to whole R&D –not only software–, then it is clear that Xilinx can get the upper hand. Looking at the R&D job listings, it is also clear that Xilinx is moving into that direction. The question then is whether Xilinx has the structure and the drive to achieve such a transformation successfully.

Related posts:

1. What to read in Xilinx’ and Altera’s third quarter results
2. Who should worry about Xilinx and Oasys partnership?