Olivier Coudert's Blog » FPGA

RIP Tier Logic

Olivier Coudert — Thu, 15 Jul 2010 22:28:27 +0000

It’s official: Tier Logic will cease to be in business on Friday July 16, 2010. The company has been trying to close its second round of funding, but it became clear last week that no short-term funding from a new VC would come, despite some due diligence by two lead investors. Since Tier Logic’s existing investor decided to not pursue on its own, it had no choice but to close the doors.

Tier Logic had a unique value proposition: you could turn its FPGA into an ASIC in a predictable time and cost. It had a working silicon and a proven production tool, and achieved to do so with spending only $20M.

It is a pity to see that a company with such a good technology and such an attracting business proposition must shut down because of lack of interest from VCs. You have to wonder which strings you have to pull in the investment community to get the attention you deserve.

Although Tier Logic will likely attempt to sell its technology to a Xilinx or an Altera, it is also quite likely that whoever the buyer is will simply buy Tier Logic’s patents to bury them. Too bad.

After Abound Logic‘s shut down 6 weeks ago, another startup showing how hard it is to be successful in FPGA.

Who should worry about Xilinx and Oasys partnership?

Olivier Coudert — Fri, 11 Jun 2010 17:51:27 +0000

Xilinx announced that it signed a multi-year strategic licensing agreement to use Oasys’ synthesis. What does that mean for the FPGA and EDA community?

Oasys’ product, RealTime Designer, is claimed to be 10x-60x faster than the competition. Among other things, it uses AIG-based optimization. This technology is best illustrated by UC Berkeley’s ABC synthesis: several FPGA startups reported that ABC boosted significantly the speed, capacity, and quality of their synthesis engines. No question that Oasys’ synthesis is competitive, at least in the FPGA world.

Xilinx is an investor into Oasys, and it has been toying with their synthesis technology for at least a year, so it’s not like they just discover each other. Xilinx has to close a software technological gap with respect to its closest competitor, Altera, and a fast, high capacity synthesis will certainly help.

Synthesis speed is key here. Until recently FPGA design was mostly an iterative process: synthesize, simulate, and debug (i.e., change in the RTL) until the performances and functionality of the design were satisfactory. That trial-and-error approach becomes impractical as the size of FPGA devices is increasing to the point that one single iteration takes hours, if not a day. Having a 10x speedup in synthesis means you can restore that familiar design iteration for a few more years.

Verification has become a bottleneck in FPGA. Simulating is used and will still be used in the future. But FPGA’s complexity requires a more complete verification methodology, like formal verification. However formal verification has trouble addressing optimization techniques heavily used in FPGA synthesis, like retiming and state re-encoding. An ABC-like optimization engine comes with a built-in formal verifier that can check independently the correctness of every incremental optimization steps performed during the optimization run. The correctness of the resulting netlist comes with a very high degree of confidence, and only the RTL description needs to be simulated.

Xilinx’ customers will benefit from that technology, and catch up with Altera’s synthesis. As for the EDA vendors selling their own FPGA synthesis, they all use or will use some flavor of AIG-based optimization. Differentiation will be done on the smartness of the high-level optimization –datapath, IPs–, the user experience (GUI), the integrated verification environment (still to be demonstrated), and of course the bottom-line: QoR –clock cycle, area, and power. The race is on.

RIP Abound Logic

Olivier Coudert — Thu, 03 Jun 2010 18:10:38 +0000

Another FPGA startup met the fate of so many others: Abound Logic is reported to have shut down this week, Wednesday June 2nd, 2010.

Abound logic, previously known as M2000, was founded by three EDA veterans who had previously started Meta Systems. Meta Systems developed the industry’s first emulation system based on custom FPGAs, which was to become the basis for the Abound Logic device after Meta Systems was acquired by Mentor Graphics in May 1996.

Abound logic’s device, the Raptor FPGA, offered in 65nm technology the capacity of 774k CLBs, each containing a 4-input LUT. This made the Raptor the largest FPGA on the market at a time.

Abound logic was in discussions to close another financing round, estimated around $20M, but one of the main tentatively new investor pulled out, which put to rest the last investment opportunities.

Is FPGA a sustainable market for EDA?

Olivier Coudert — Tue, 20 Apr 2010 23:53:13 +0000

A FPGA company makes revenue with the hardware: it sells its device, and gives away its design tools –synthesis, place-and-route. Yet the EDA industry has had success with its own (non-free) FPGA synthesis solutions. For good reasons: in its days, Synplicity’s Synplify was the best FPGA synthesis out there. Synopsys acquired Synplicity two years ago, but it was more to get a comprehensive emulation solution than pushing FPGA synthesis. Mentor Graphics is still invested in FPGA synthesis with Precision, and competes head to head with Xilinx’ XST and Altera’s Quartus.

In a world where FPGA software design is expected to be free (or very cheap, compared to it ASIC counterpart), is there still a market for EDA companies to sell their FPGA solutions? Synplicity stopped growing after it built its success on FPGA synthesis. Is that the fate of EDA for FPGA?

There are several forces at play here: device complexity, software complexity, and know-how.

The complexity of FPGA starts to rival that of ASIC’s. The largest FPGA devices contain 100,000’s of LUTs and registers, 1000’s of DSP components, and are equivalent to 1+ million gate designs. The increasing device size requires faster synthesis and larger capacity. It also strains verification because simulation costs are augmenting accordingly. The days were a designer could complete her FPGA project with a simple write-RTL/synthesize/simulate/fix iterative flow are gone.

FPGA companies differentiate with their devices’ speed, capacity, and power consumption. But beyond the raw hardware features, software to design FPGA has become a key for success. Altera learnt the lesson the hard way 10 years ago when it released software that was not ready: Altera quickly lost its top customers to Xilinx, while it could have become the undisputed #1 FPGA vendor. Some FPGA startups in the past could not get off the ground because they fail to deliver good synthesis for their device. Closer to us, we have heard about Tabula’s chronic problems to bring up its synthesis before it finally announced its device earlier this year. And Abound Logic’s huge netlist has stretched the capacity of today’s FPGA synthesis.

Altera has now a software powerhouse, and is meticulous about its software design and testing. Xilinx is currently going through a major overhaul of its software to catch up with its main competitor. There is no question that software is taken very seriously by the two vendors –they both have a couple hundreds engineers dedicated to provide customers with a full design tool suite.

So does EDA has any future in FPGA synthesis? There will always be FPGA startups looking for an OEM with Synopsys and Mentor, but this is not enough. The EDA industry must showcase a comprehensive FPGA development environment that will cover design, synthesis, and verification:

Verification is becoming ever more costly for FPGAs, as it already is for ASICs. Formal verification for FPGA is still embryonic –FPGA synthesis uses retiming and FSM re-encoding that makes formal verification quite difficult.
Synthesis of complex systems with a large IP spectrum is an area of expertise that EDA must leverage. Also EDA could provide a much-needed improvement in power management.
As for design, EDA must seize on the FPGA community’s ability to adopt new methodologies much faster than the ASIC community. ESL, SystemC, and C/C++ as hardware description languages are the right direction.

If EDA wants to compete with the few hundred software engineers of Xilinx and Altera, it needs to deliver a best-in-class and innovative FPGA design environment. Else it will end up as a no-growth by-product of ASIC synthesis.

Can Tabula and Tier Logic be successful?

Olivier Coudert — Fri, 12 Mar 2010 13:08:03 +0000

The past two weeks were pretty interesting if you follow FPGAs. Yes, Xilinx and Altera kept upping their target to Wall St., but that is not where the excitement came from. It came from the recent announcements of two startups, both created in 2003 and heavily funded. Tabula released its long-awaited device, which goes by the sexy name of “Spacetime”. And Tier Logic left its stealth mode this week to announce its own device, “TierFPGA”.

The dominant factor in classical FPGA architecture is the interconnect: most of the die area is taken by the wires and the interconnect switches and muxes. If you can somehow reduce the area dedicated to interconnect, you can augment the logic density and lessen the cost of the device. Tabula and Tier Logic pitch a 3D architecture to address the interconnect bottleneck, albeit in very different flavors.

Tabula innovative design is based on its ability to reconfigure itself, up to 8 times with a clock running at 1.6GHz. At each cycle a cell can change its functionality, its latch configuration, and its interconnect. The time-multiplexing increases the amount of logic that can be fit on the same area. It is like having 8 layers (or “folds”) of cells stacked on top of each other along a time axis, with very short connection between cells at the same (x,y) coordinate but in two adjacent folds. At each cycle one jumps to the next fold and feeds the new configured logic with the results of the previous fold. Tabula claims they increase the logic density by 2.5x compared to classical FPGA architectures.

Tier Logic’s design idea is to place the SRAM cells that configure the interconnect muxes on top of the routing layers, instead of having them distributed throughout the logic die area. Doing so leaves more room for logic cells, increasing the cell density by about 50% according to the company. The design flow will not throw anybody off: it uses Mentor’s Precision for synthesis, and is followed by Tier Logic’s mapping and P&R.

A big plus touted by Tier Logic is the ability of moving painlessly from their device to an ASIC. Simply replace the interconnect configuration SRAM cells at the top with metal, and voila, you obtain an ASIC with no change in timing. This is a simple, predictable process: it takes about 4 weeks to go from the SRAM configuration to a top-layer mask, and you do not need to go through a timing closure flow again, which means a non-recurring engineering cost of about $50k. This is a real bargain when you consider that moving from FPGA to ASIC usually requires a redesign that can take as long as 9 months.

So who of Tabula and Tier Logic is best positioned to challenge the duopoly Xilinx/Altera?

Tabula made it clear that they are aiming at the high-end of the FPGA market. There are a number of FPGA startups that targeted the same niche, and none survived. One reason is that it is easy for Xilinx and Altera to increase the size of their device, by simply moving to the next technology node. Tabula’s design is innovative and pushes the limits, but how far is too far? It is unclear whether the company can deliver the design tools to match their device’s challenges –they went through a complete reset a few years ago, replacing the whole software team. Verifying a device that can reconfigure itself 8 times in a loop may be another challenging problem. Increased density is obtained by continuous reconfiguration, which means extra power consumption: is it still an acceptable tradeoff? Last but not least, with 100+ people in the US, it is a well-known fact in the Silicon Valley that Tabula burns cash fast, and their funding of $106 millions so far is about to come short.

Tier Logic’s FPGA can reduce the cost of the device for the same density. But their compelling value proposition is really their FPGA to ASIC translation. This is what Altera’s HardCopy was supposed to be, a seamless and risk-free migration from FPGA to ASIC. For anybody that wants to design an application and then migrate to a low/medium volume ASIC production, this could be the most cost efficient solution. I do not know the inside story regarding the financial aspect, but their business proposal looks more solid.

So who do you think has a chance here? Let’s meet again in 3-4 quarters and see how the two companies are doing.

What EDA needs to change for 2020 success?

Olivier Coudert — Sat, 07 Nov 2009 01:24:52 +0000

ICCAD’09 was a fairly good vintage. It started Monday morning with an excellent keynote from Hamid Pirahesh about cloud computing. The same day in the afternoon, a more EDA-focused discussion was initiated by Jim Hogan and Paul McLellan (slides can be found here), asking the question “What EDA needs to change for 2020 success?”

Paul rightly emphasized three trends. The first one is well know: the continuously rising cost of IC designs, about $50M for today’s 45nm node. The second trend is that the fastest growing part of the design cost is software –more than half of the overall cost, Paul even claiming close to 2/3 of the overall cost. The third trend is an increasingly fragmented consumer market: the number of end products goes into the 10’s of billions, but these products are declined in many more different kinds, which means that most of them are shipping in smaller individual volumes.

Source: Morgan Stanley, Economy + Internet Trends, Web 2.0 Summit, San Francisco, Oct 2009.

This is bad news for EDA as we know it: the rising cost of design can no longer be justified if the number of units does not grow fast enough (a $50M chip starts to make sense only if it is produced for 250M units and more). Also EDA has been slow to climb up the food chain and proposes solutions for software design, which dominates the overall chip design cost.

Rising IC design cost and smaller number of units is the call for FPGA to growth even faster. Mobile applications require FPGA to do much better in terms of power consumption, but this is a hot topic (no pun intended) drawing a lot of attention and investment, and some competitive solution will emerge in the next few years. So EDA, which makes its bread and butter on IC design, should better re-align its growth strategy on software, embedded systems, HW/SW co-design, and verification. Else EDA will continue to shrink to only service the few that can still afford chip design.

The end product, as a SoC, is a puzzle where the designer mostly assembles existing cores and IPs, and decides of the tradeoff between the software and hardware parts, based on flexibility and cost factors.

I see two strong needs that EDA could build its growth on. One is functional validation of the whole system –software plus hardware. EDA has started to address the issue, even though it is still short of proposing a scalable and automated environment. To functional validation, I would also add functional flexibility: how much of the behavior can be upgraded thanks to the software part? The other need is a design navigator that would estimate the speed, area, power consumption, and cost of a SoC by exploring alternatives between cores (ARM, MIPS, etc), IPs, FPGA, and software.

Last but not least, the eternal question of an EDA serving a $250B semiconductor industry, but making less than $5B. The time-based license model has only served the interests of the semiconductor companies, to the expenses of R&D investment in EDA. Claiming a lack of innovation in the EDA industry is sometimes fair, but EDA should also innovate in business solutions instead of cannibalizing itself by cutting costs to only survive another quarter. The semiconductor industry needs a healthy EDA if it wants to address the system-level design challenges of the next 10 years. Unless, of course, a new player coming from the software world with the experience of scalable systems signs the death of the EDA industry as we know it.

How can Xilinx improve its bottom line

Olivier Coudert — Fri, 30 Oct 2009 22:45:05 +0000

Last week I wrote a post discussing Xilinx and Altera Q3’09 results, and I mentioned Xilinx’ operation margin consistently trailing Altera’s by 3-4%. I had a few emails regarding that gap, and why that gap would be closed eventually. Let me address this topic with this post.

Comparing the yearly fiscal exercises directly would be biased (Xilinx’ fiscal year end on March 31^st, and Altera’s fiscal year on Dec 31^st). Instead we can look at a quarter by quarter comparison, even though that can be too low a level. Better is to look for ttm (trailing twelve months) comparison to smooth out the local variations.

Source: Yahoo! Finance. All figures in thousands.

One can see that Altera’s operating margin is overall better. Also in their respective Q3’09 revenue reports, Xilinx expects its Q4’09 gross margin to improve to 62-63%, and Altera sees his to be 67-68%. So a 3-4% operating margin gap will remain, which is significant.

On the other hand, Xilinx quotes 3145 full time employees, and Altera 2760. This means that a Xilinx employee brings back revenue about 26% higher than an Altera employee! So it all boils down to the question: how can Xilinx be more cost efficient?

One of the differences is the way software is developed. Altera’s software is mostly done in their technology center of Penang, Malaysia, with a very small core technology group in Toronto, Canada. Xilinx’s software team is mostly in the US, and only 5% of the team is in their R&D facilities in Hyderabad, India. A back-of-the-envelop calculation shows that if Xilinx had the same software team but with a US/India ratio 1/3-2/3, which is a healthy ratio for a company that can leverage its India facility, Xilinx would improve its operating margin by one point.

If you extend the same reasoning to whole R&D –not only software–, then it is clear that Xilinx can get the upper hand. Looking at the R&D job listings, it is also clear that Xilinx is moving into that direction. The question then is whether Xilinx has the structure and the drive to achieve such a transformation successfully.

The formal verification market is still untapped

Olivier Coudert — Mon, 19 Oct 2009 16:19:31 +0000

Functional verification is a major bottleneck in the chip design cycle. Any misstep in closing the functional correctness of a digital system costs millions of dollars in redesign, additional testing, and silicon respins. One can argue at length about its actual cost, but people in the industry usually agree that functional verification takes between 40 and 70% of a project’s labor, and about 50% of the total cost. The recent announcement of Synopsys and Freescale to broaden their collaboration to cut IC verification says it all: the two partners intend to manage “the ever-increasing cost of verification, which can encompass up to 75 percent of the total cost of product development”.

Getting actual figures about the size of the functional verification market proves to be elusive because of the way the products are tied to synthesis license deals, and because of the lack of independent analysts in EDA. Still, the simulation and emulation market of digital systems can be estimated to be at least five times larger than today’s formal verification market. But simulation can only take you so far, so one wonders why formal verification does not have a larger share. Is it because the technology is limited, or because the market is not ready?

Equivalence checking

Equivalence checking (EC) consists of verifying that a netlist implements the behavior specified by a RTL description, or that two netlists are equivalent. Historically, EC is the first industrial formal verification tool brought to the ASIC world. Cadence’s Conformal is still the reference (about 60% of the market), with Synopsys’ Formality coming second.

EC’s technology is very mature, but this does not mean no further progress is necessary. Flip-flop matching, the primarily step that consists of determining the pairs of flip-flops that need to be compared, is expected to be done quickly and automatically, with no manual guidance. Datapath verification remains a major challenge, and proving the correctness of merged arithmetic automatically is still an open problem. Last but not least, debugging is a very complicated task. Incremental verification and rectification techniques can be quite useful to help pinpointing the functional issue.

Model checking and property verification

Model checking and property verification are still a fraction of the formal verification market, with many players on the field. There are two obstacles for a larger usage of the approach. The first one is that it can be complicated to write a FSM or property that captures a particular behavior. SVA (System Verilog Assertions), OVL (Open Verification Library), and PSL (Property Specification Language) help in that regard, but they need to be more systematically used in the design community. The second obstacle is that model checking techniques can only solve relatively small problem instances. This is why some go with hybrid verification techniques (read: may be incomplete), like Magellan or 0-in, while other stick with complete formal methods, like Jasper and OneSpin.

Because writing properties can be so complicated, specialized branches grew to address specific needs, as shown below.

IP verification. With SoCs using IPs from many different sources, verifying the compliance of these IPs with respect to standard interfaces (e.g., PCI or USB) in the context of the application is crucial. Conformal, with its verification IP portfolio, is in a good position to address the problem. Also OneSpin is known to have interesting technology in that space, even though they are not pushing it at the moment.
Timing verification. Incorrect timing constraints can lead to missing a target clock cycle, or worse, to a chip failure. Verifying timing exceptions (false paths and multi-cycle paths), as well as CDC (Clock-Domain Crossing), has become a center of attention. It is still unclear how big the market is. However several discussions with IC design companies led me to believe that verifying a set of timing exceptions (usually in the order of 10,000 SDC constraints) save one month work of an engineer. Automation and speed are keys here. Atrenta, Real Intent, and 0-in propose interesting solutions in that space.
Power verification. When doing power gating, one needs to verify that the application is powered back up properly. Integration with UPF or CPF provides the required automation. Conformal and CPF have an edge in that field.
Sequential clock gating verification. Traditional (combinatorial) clock gating is well supported by EC tools. Sequential clock gating exploits sequential dependencies to derive additional gating conditions, which can be used to save more dynamic power. It has been made popular by Calypto –Envis is also proposing a similar technique at the netlist level. Sequential clock gating correctness cannot be expressed easily with SVA or OVL without making the verification task extremely complex, which explained why specialized verification techniques have been developed.

Where formal verification will grow

Formal verification is no longer limited to ASICs: complex systems –SoC, FPGA, and HW/SW co-design— will benefit dramatically from better formal verification techniques if they are deployed adequately.

With the ever-growing size of FPGAs (Altera’s Stratix IV packs 820k logic elements, and Xilinx’ Virtex-6 has up to 750k logic cells), it is clear that simulation will no longer be sufficient to validate the correctness of programmable logic devices. The need for FPGA EC is real, and this requires complete automation and full support for retiming –OneSpin’s 360 EC FPGA has shown some competitive solution in that space. Also note that IP verification and timing verification apply to the FPGA designs too. The real question is whether FPGA designers are willing to pay for formal verification tools.

IP verification, and verifying the correctness of a SoC using IPs, is certainly a very strong driver for more sophisticated formal verification solutions. Power verification will become part of the ASIC design flow, as EC is part of the synthesis flow. Timing verification is still looking for its footing in the design flow –one question is the debug environment, which is still relatively limited, e.g., to showing waveforms.

Looking forward, formal verification techniques can be used (and have been used) in other fields than circuit design. Any critical digital system can benefit from formal verification techniques –transportation, medical equipments, security and privacy applications. The automotive industry is one of the most obvious targets. Cars are ubiquitous, they contains more and more electronics (representing about 30% of the end price today), and a functional bug can have very costly consequences. Cars rely on digital systems for anything from optimizing their engine’s efficiency to navigation systems, entertainment, and on-board diagnosis. Soon the intra-vehicle, vehicle-to-vehicle, and vehicle-to-roadside networking will fuel innovative products, driving the needs for fast development and the highest possible level of correctness. The EDA industry is taking notice, and Mentor has certainly taken the lead there. Whether they provide the adequate functional verification framework is another matter.

Formal verification will extend its reach by addressing the hard problems of EC (datapath verification, and retiming for FPGA), by being seamlessly integrated in the synthesis flow (power and timing exception verification), and by providing practical solutions to IP and hybrid HW/SW design verification.

What to read in Xilinx’ and Altera’s third quarter results

Olivier Coudert — Thu, 15 Oct 2009 16:03:54 +0000

This week Xilinx and Altera released their September results (Q2FY10 and Q3FY09 respectively). The bottom line is shown below (all numbers in $M).

Source: Xilinx and Altera financial reports, and Yahoo! Finance

Xilinx’ quarterly income of $64M (0.23$/share) beats Wall Street’s expectation of 0.19$/share. Altera’s quarterly income of $56.7M (0.19$/share) meets Wall Street’s expectation. Both companies expect a 6-10% revenue increase for Q4’09 from previous quarter. Xilinx expects its Q4’09 gross margin to improve to 62-63%, and Altera sees his to be 67-68%.

Both companies are benefiting equally of an improving economy. Altera is seeing a large part of its revenue coming from new products (60% for Q3’09), as opposed to Xilinx (31% in Q3’09).

I would give a slight edge to Altera, given its recent offer of high-performance new devices, and its operation margin consistently ahead of Xilinx’. One day Xilinx should be able to close the 3-4% operation margin gap it has with Altera, but until then it will not be as efficient and dynamic as Altera. I will discuss in another post how Xilinx can close this gap.

Why FPGA startups keep failing

Olivier Coudert — Wed, 16 Sep 2009 01:16:07 +0000

The FPGA market has been entrenched in a duopoly for a number of years now. In 2008, according to Gartner Inc., Xilinx Inc. and Altera Corp. hold together 87% of the market of programmable logic (51.2% and 35.5% respectively). The rest of the market is covered mostly by Actel Corp. and Lattice Semiconductor Corp., about 6% each.

There have been attempts to challenge the comfortable equilibrium between the two FPGA giants Xilinx and Altera. Indeed, the number of FPGA startups increased after the 2000 downturn. Over the past 7-9 years it looks like VCs founded FPGA startups one after another. Beside the attraction of a programmable logic market that has been growing a healthy 8-11%, compared to a stalled ASIC market, the availability of engineers and executives from the most prestigious firms (Xilinx, Altera, Intel, LSI, etc) may have been a factor in driving more VC money in FPGA startups.

However, most of these startups die after a few years. The list includes Chameleon Systems, which died in 2002; the promising Velogix, formerly known as Flexlogics, created in 2002, and which eventually ran out of funds; Ambric Inc, whose assets were acquired by Nethra in 2008; Mathstar Inc, which stopped operating in 2008; and CSwitch, which closed the doors this summer.

Still, there are a number of active FPGA startups. Among the most notable, one can cite Abound Logic, formerly known as M2000, which started back in 1996, and claims high density FPGA for high-end customers; Tabula, which had to go through a full reset, raised a considerable amount of money, and from which a product is expected sometime later this year; eAsic, still on going after a few misfires; Achronix, which promises a throughput of up to 1.5GHz; SiliconBlue, which aims at low power application; and certainly more companies lesser known or still in stealth mode, like Tier Logic.

All these attempts failed so far to jeopardize the duopoly Xilinx/Altera. Why is it so? Any new venture needs to come with a significant differentiation if it wants to challenge the existing competitors. Many FPGA startups came out with claims of higher densities and better clock cycles. But regardless of how you look at FPGA architectures, it is not a fundamentally difficult hardware to design, especially with the profusion of expert layout engineers that exists in this field. One cannot expect a revolution that would bring a 10x better density. Startups’ claims of 2x or higher density eventually have to face the harsh reality that Xilinx and Altera just need to move to the next technology node to match or substantially reduce the performance claims. Moving to the next technology node is certainly more accessible to a Xilinx or an Altera giant than to a startup for which a new mask can consume half of a second- or third-round financing. The bottom line is that displacing a well established vendor requires more than a 2x density improvement. First of all, you need to make sure you have the software that can exploit that extra density to deliver better results; second, for most applications, density becomes secondary as long as it fits on a board, and the ever-increasing size of the Xilinx and Altera devices makes capacity a hard sell, except possibly for a small fraction of the high-end customers; third, capacity is even more secondary when power consumption comes into play.

In a consumer electronics market more and more dictated by portable and wireless products, power is a factor that is more important that raw performance. In that regard, SiliconBlue looks the best positioned to distinguish itself from its peers, and proposes a value that both Xilinx and Altera cannot meet, at least for the moment. They are the ones to watch.