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ICCAD’09 was a fairly good vintage. It started Monday morning with an excellent keynote from Hamid Pirahesh about cloud computing. The same day in the afternoon, a more EDA-focused discussion was initiated by Jim Hogan and Paul McLellan (slides can be found here), asking the question “What EDA needs to change [...] Continue reading What EDA needs to change for 2020 success? Last week I wrote a post discussing Xilinx and Altera Q3’09 results, and I mentioned Xilinx’ operation margin consistently trailing Altera’s by 3-4%. I had a few emails regarding that gap, and why that gap would be closed eventually. Let me address this topic with this post. Comparing the yearly fiscal exercises directly would be [...] Continue reading How can Xilinx improve its bottom line Functional verification is a major bottleneck in the chip design cycle. Any misstep in closing the functional correctness of a digital system costs millions of dollars in redesign, additional testing, and silicon respins. One can argue at length about its actual cost, but people in the industry usually agree that functional verification takes [...] Continue reading The formal verification market is still untapped This week Xilinx and Altera released their September results (Q2FY10 and Q3FY09 respectively). The bottom line is shown below (all numbers in $M). Source: Xilinx and Altera financial reports, and Yahoo! Finance Xilinx’ quarterly income of $64M (0.23$/share) beats Wall Street’s expectation of 0.19$/share. Altera’s quarterly income of $56.7M (0.19$/share) meets [...] Continue reading What to read in Xilinx’ and Altera’s third quarter results The FPGA market has been entrenched in a duopoly for a number of years now. In 2008, according to Gartner Inc., Xilinx Inc. and Altera Corp. hold together 87% of the market of programmable logic (51.2% and 35.5% respectively). The rest of the market is covered mostly by Actel Corp. and Lattice Semiconductor Corp., about [...] Continue reading Why FPGA startups keep failing |
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