Instead, I have chosen to share my absolutely non-exhaustive, completely biased view of DAC. I will then publish a couple of posts focused on specific themes in the next few days.

Attendance

The 47^th DAC was held June 13-18 at the Anaheim Convention Center in California. The preliminary attendance numbers are reported as follow:

• Total full conference: 1554
• Total exhibit attendees: 3444 (24% international)
• Exhibitors, visitors, and guests: 2557
• Total attendees: 6001

The final attendance numbers are usually a few percent higher.

For a fair comparison, I pulled out the preliminary attendance numbers of the past conferences. I was first fooled by the way the numbers were labeled this year –see the comments below, and a big thanks to Sean to bring me the correct interpretation. The table below shows the correct data, excluding booth staff. It shows a sharp decline (33%) of the total attendance compared to last year in San Francisco. Not having DAC in San Francisco means higher cost for most of the attendees –many of them are from the Silicon Valley–, which is clearly reflected in the attendance numbers.  But if we compare this year’s numbers with the 2008 DAC venue held at the same location, we see the same sharp decline (28%). Note the drop in exhibits-only attendees (-41% w.r.t. 2009, -21% w.r.t. 2008), not a good sign as this number captures most of the customer audience.

DAC preliminary attendance numbers (not including booth staff)

This year’s DAC comes after one of the worst recession, but looking forward to a very strong semiconductor growth in 2010 and 2011, which should eventually translate into a mildly better business for EDA. The exhibition was well attended on Monday, with a sharp decline on Wednesday –lots of people left by that time.

The buzz

With Cadence’s EDA360 campaign in the background, and the fresh acquisitions of Denali by Cadence and Virage Logic by Synopsys, it felt that IP was the buzzword of the day. IP design here, IP verification there, verification IP everywhere, the overall SoC design looked like an IP integration problem that EDA was gearing up to take on. Embedded software and ESL were also showcased by Cadence and Mentor Graphics as part of their SoC focus.

Verification

There was a booth dedicated to UVM/OVM (Universal Verification Methodology/Open Verification Methodology). These methodologies offer open and interoperable verification solutions. They both support multiple languages and simulators, and enable verification IP, so critical to SoC design. The message was well received and had a strong attendance.

Still on the verification side, new products and startups are trying to repeat the success of Certess (acquired by SpringSoft last year). Advanced formal verification tools (e.g., property checkers) are slow to find acceptance by the design community. Instead these new products and startups leverage the existing test bench and simulation methodology in place to produce better coverage or faster simulation. Notably missing in this space was NuSym, a no-show at this year’s DAC, confirming the rumors that the startup that demonstrated “intelligent” simulation two years ago is actively looking for a buyer.

The whole simulation and emulation space was strong. Mentor’s Veloce is showing impressive numbers, and is ready to take on Cadence’s Palladium. Eve will likely take notice, and this may bring it closer to Synopsys.

Magma’s Tekton offers sign-off quality multi-mode/multi-corner static timing analysis for multi-million gate circuits. The tool has been designed from the ground up, and tailored for multi-threading and distributed systems. It is a clear competitor to Synopsys’ PrimeTime, even though running PrimeTime *is* the signoff for most customers.

Design and implementation

On the P&R and backend side, nothing really stood out. Synopsys clearly gained in QoR, Mentor’s momentum with Sierra’s Olympus is still strong, and Magma keeps lagging behind, especially in runtime. Atoptech and Azuro, although showing pretty good numbers (verified at customers’), are still considered more like add-ons that comprehensive solutions. This segment looks more and more commoditized, and only the high-end (20nm and below) and 3D seem to offer new growth opportunities in that space.

Oasys, the darling of last year’s DAC, did not make as much as a splash this time, despite its recent announcement with Juniper Networks and Xilinx. Nobody question the speed and capacity of their tool, as well as the clock cycle it can achieve. But some raised concerns regarding the area of their netlists for ASIC.

On the fringe

This is the “stuff I liked that may be too small to be noticed”, even more so since two of these three companies didn’t have a booth at DAC…

Low power is still under-represented, even though power gets worse with smaller geometries, and power management remains mostly a very manual process. In that space I liked Docea Power, which can simulate system-level models to analyze power consumptions and thermal behaviors. System-level analysis can bring the biggest power savings. It also has a significant impact on the packaging, which is still a domain where conservative approaches are preferred to more cost-efficient, but riskier, choices.

A comprehensive system-level design framework is really an IDE (Integrated Development Environment) for SoC, where hardware and software can be designed together, written and simulated together, and where the HW/SW tradeoffs can easily be explored. IDEs have been used in software for a long time, but are a novelty to hardware designers. Sigasi proposes an IDE for VHDL –what Microsoft’s Visual Studio is to C++. Although this is still light-years away from a SoC IDE, this is a hint into the future of writing RTL.

We heard several claims that cloud computing is coming to EDA (or the converse?). Xuropa best illustrates that (slow) move. They provide turn-key online community solutions for the electronic design industry. Their main customers, Cadence and Synopsys, are using the services for CRM and virtual demo only. But Xuropa could become a platform that enables collaborative design in the cloud, providing secured access to a multi-vendor flows. More on this in a future post.

Last words

I felt that there was a lot of system-centric messages (best captured by EDA360), and attempts at rising the abstraction level for higher productivity. EDA vendors are forced to see the big picture –full system design, software and hardware together. But as pointed out by Steve Jones (TI) at Cadence’s Silicon Realization Luncheon, EDA is still missing out on two important parts of the SoC design. One is that customers want a first-silicon that is functionally operational, and Steve singled out the need for useable verification IP –UVM/OVM is a step in the right direction. The other is analog –mixed-signal design is the rule, and there is no good integration there.

Related posts:

1. Did you feel the tremor? The 2010 challenges for EDA
2. The formal verification market is still untapped
3. Has formal verification technology stalled?

Oasys’ product, RealTime Designer, is claimed to be 10x-60x faster than the competition. Among other things, it uses AIG-based optimization. This technology is best illustrated by UC Berkeley’s ABC synthesis: several FPGA startups reported that ABC boosted significantly the speed, capacity, and quality of their synthesis engines. No question that Oasys’ synthesis is competitive, at least in the FPGA world.

Xilinx is an investor into Oasys, and it has been toying with their synthesis technology for at least a year, so it’s not like they just discover each other. Xilinx has to close a software technological gap with respect to its closest competitor, Altera, and a fast, high capacity synthesis will certainly help.

Synthesis speed is key here. Until recently FPGA design was mostly an iterative process: synthesize, simulate, and debug (i.e., change in the RTL) until the performances and functionality of the design were satisfactory. That trial-and-error approach becomes impractical as the size of FPGA devices is increasing to the point that one single iteration takes hours, if not a day. Having a 10x speedup in synthesis means you can restore that familiar design iteration for a few more years.

Verification has become a bottleneck in FPGA. Simulating is used and will still be used in the future. But FPGA’s complexity requires a more complete verification methodology, like formal verification. However formal verification has trouble addressing optimization techniques heavily used in FPGA synthesis, like retiming and state re-encoding. An ABC-like optimization engine comes with a built-in formal verifier that can check independently the correctness of every incremental optimization steps performed during the optimization run. The correctness of the resulting netlist comes with a very high degree of confidence, and only the RTL description needs to be simulated.

Xilinx’ customers will benefit from that technology, and catch up with Altera’s synthesis. As for the EDA vendors selling their own FPGA synthesis, they all use or will use some flavor of AIG-based optimization. Differentiation will be done on the smartness of the high-level optimization –datapath, IPs–, the user experience (GUI), the integrated verification environment (still to be demonstrated), and of course the bottom-line: QoR –clock cycle, area, and power. The race is on.

Related posts:

1. Is FPGA a sustainable market for EDA?
2. How can Xilinx improve its bottom line
3. What to read in Xilinx’ and Altera’s third quarter results

In a world where FPGA software design is expected to be free (or very cheap, compared to it ASIC counterpart), is there still a market for EDA companies to sell their FPGA solutions? Synplicity stopped growing after it built its success on FPGA synthesis. Is that the fate of EDA for FPGA?

There are several forces at play here: device complexity, software complexity, and know-how.

The complexity of FPGA starts to rival that of ASIC’s. The largest FPGA devices contain 100,000’s of LUTs and registers, 1000’s of DSP components, and are equivalent to 1+ million gate designs. The increasing device size requires faster synthesis and larger capacity. It also strains verification because simulation costs are augmenting accordingly. The days were a designer could complete her FPGA project with a simple write-RTL/synthesize/simulate/fix iterative flow are gone.

FPGA companies differentiate with their devices’ speed, capacity, and power consumption. But beyond the raw hardware features, software to design FPGA has become a key for success. Altera learnt the lesson the hard way 10 years ago when it released software that was not ready: Altera quickly lost its top customers to Xilinx, while it could have become the undisputed #1 FPGA vendor. Some FPGA startups in the past could not get off the ground because they fail to deliver good synthesis for their device. Closer to us, we have heard about Tabula’s chronic problems to bring up its synthesis before it finally announced its device earlier this year. And Abound Logic’s huge netlist has stretched the capacity of today’s FPGA synthesis.

Altera has now a software powerhouse, and is meticulous about its software design and testing. Xilinx is currently going through a major overhaul of its software to catch up with its main competitor. There is no question that software is taken very seriously by the two vendors –they both have a couple hundreds engineers dedicated to provide customers with a full design tool suite.

So does EDA has any future in FPGA synthesis? There will always be FPGA startups looking for an OEM with Synopsys and Mentor, but this is not enough. The EDA industry must showcase a comprehensive FPGA development environment that will cover design, synthesis, and verification:

• Verification is becoming ever more costly for FPGAs, as it already is for ASICs. Formal verification for FPGA is still embryonic –FPGA synthesis uses retiming and FSM re-encoding that makes formal verification quite difficult.
• Synthesis of complex systems with a large IP spectrum is an area of expertise that EDA must leverage. Also EDA could provide a much-needed improvement in power management.
• As for design, EDA must seize on the FPGA community’s ability to adopt new methodologies much faster than the ASIC community. ESL, SystemC, and C/C++ as hardware description languages are the right direction.

If EDA wants to compete with the few hundred software engineers of Xilinx and Altera, it needs to deliver a best-in-class and innovative FPGA design environment. Else it will end up as a no-growth by-product of ASIC synthesis.

Related posts:

1. Why FPGA startups keep failing
2. The formal verification market is still untapped
3. Who should worry about Xilinx and Oasys partnership?

The dominant factor in classical FPGA architecture is the interconnect: most of the die area is taken by the wires and the interconnect switches and muxes. If you can somehow reduce the area dedicated to interconnect, you can augment the logic density and lessen the cost of the device. Tabula and Tier Logic pitch a 3D architecture to address the interconnect bottleneck, albeit in very different flavors.

Tabula innovative design is based on its ability to reconfigure itself, up to 8 times with a clock running at 1.6GHz. At each cycle a cell can change its functionality, its latch configuration, and its interconnect. The time-multiplexing increases the amount of logic that can be fit on the same area. It is like having 8 layers (or “folds”) of cells stacked on top of each other along a time axis, with very short connection between cells at the same (x,y) coordinate but in two adjacent folds. At each cycle one jumps to the next fold and feeds the new configured logic with the results of the previous fold. Tabula claims they increase the logic density by 2.5x compared to classical FPGA architectures.

Tier Logic’s design idea is to place the SRAM cells that configure the interconnect muxes on top of the routing layers, instead of having them distributed throughout the logic die area. Doing so leaves more room for logic cells, increasing the cell density by about 50% according to the company. The design flow will not throw anybody off: it uses Mentor’s Precision for synthesis, and is followed by Tier Logic’s mapping and P&R.

A big plus touted by Tier Logic is the ability of moving painlessly from their device to an ASIC. Simply replace the interconnect configuration SRAM cells at the top with metal, and voila, you obtain an ASIC with no change in timing. This is a simple, predictable process: it takes about 4 weeks to go from the SRAM configuration to a top-layer mask, and you do not need to go through a timing closure flow again, which means a non-recurring engineering cost of about $50k. This is a real bargain when you consider that moving from FPGA to ASIC usually requires a redesign that can take as long as 9 months.

So who of Tabula and Tier Logic is best positioned to challenge the duopoly Xilinx/Altera?

Tabula made it clear that they are aiming at the high-end of the FPGA market. There are a number of FPGA startups that targeted the same niche, and none survived. One reason is that it is easy for Xilinx and Altera to increase the size of their device, by simply moving to the next technology node. Tabula’s design is innovative and pushes the limits, but how far is too far? It is unclear whether the company can deliver the design tools to match their device’s challenges –they went through a complete reset a few years ago, replacing the whole software team. Verifying a device that can reconfigure itself 8 times in a loop may be another challenging problem. Increased density is obtained by continuous reconfiguration, which means extra power consumption: is it still an acceptable tradeoff? Last but not least, with 100+ people in the US, it is a well-known fact in the Silicon Valley that Tabula burns cash fast, and their funding of $106 millions so far is about to come short.

Tier Logic’s FPGA can reduce the cost of the device for the same density. But their compelling value proposition is really their FPGA to ASIC translation. This is what Altera’s HardCopy was supposed to be, a seamless and risk-free migration from FPGA to ASIC. For anybody that wants to design an application and then migrate to a low/medium volume ASIC production, this could be the most cost efficient solution. I do not know the inside story regarding the financial aspect, but their business proposal looks more solid.

So who do you think has a chance here? Let’s meet again in 3-4 quarters and see how the two companies are doing.

Related posts:

1. RIP Tier Logic
2. Why FPGA startups keep failing
3. RIP Abound Logic

My claim is that formal verification has reached a plateau from both the core technology and business point of view.

Yet that does not mean there is no progress! There is a world between creating a brand new technology and using it for an actual working product. This is what the Jasper, Real Intent, Atrenta, OneSpin, and many others are doing, as they creatively use these core technologies to propose new applications.

From the technological point of view, we have experienced steady improvements in many aspects –equivalence checking (EC), sequential verification, abstraction and refinement, etc. The scope of application of formal verification techniques has dramatically increased for the past few years. It has of course benefited from more powerful hardware –faster CPU, larger memory, multi-threading, distributed systems, FPGA. It also benefited from the skilled engineering of the core technologies, to the credit of the many private companies in the field.

But there is no recent verification tool that has been enabled by any new core technology. Nothing wrong with this, it is partially the consequence of a mature industry, where most of the effort goes into improving the customer experience and helping him integrating verification and design/synthesis flow.

When Randy Bryant published his BDD paper in 1986, he revolutionized the field of formal verification with a technology that could address problems previously out of reach. When EC switched from BDD to SAT solvers nearly 10 years ago, it made possible verifying multi-million gate designs against their RTL description. Bounded model checking became a practical approach to sequential property verification. These were disruptive technologies. Where is the next leap?

From the business point of view, force is to admit that the formal verification market has been pretty stable. Most of the ever-increasing design cost is taken by verification, but that does not translate into a fast growing formal verification market. Instead, the more and more daunting verification task benefits simulators more than formal tools. Yes, customers are slow to move to a different verification flow. Yes, the formal verification industry, as the rest of EDA, struggles to find a business model that would bring back a much needed growth. But which application or technology will bring enough value to make the ratio simulation/formal in favor of the later?

Regarding the simulation vs. formal debate, I would recommend reading Chris Wilson’s comment. He agrees with me that formal verification has had a relatively low return on investment. He then argues that simulators will remain the main verification solution, with formal verification technologies under the hood to speed up simulation, to increase coverage, and to help debugging. He may well have a point here.

One aspect that everybody agrees on is that debugging is still a bottleneck in the verification industry. Why does a design fail its functional requirement? Having a counter example (e.g., a sequence of inputs that disproves a safety property) is often not sufficient: the complexity and length of the counter example can make pinpointing the design error very difficult. A failing liveness property cannot be revealed with a finite sequence of inputs. Similarly, there is no tool that provides consistent debugging information explaining why a statement of a RTL description is unreachable. Formal verification techniques can certainly help here, and there are a few available products aiming at the problem.

In conclusion, formal verification as an industry has matured, but is still looking for the market share it deserves. I think there are a lot of opportunities to grow the market. Success may come as an enabler of a better, faster, high coverage, simulation. I rather believe it will come when formal verification allows software and hardware to be verified and debugged in a common, continuous, design flow. And this requires some major technical innovation.

Related posts:

1. Has formal verification technology stalled?
2. The formal verification market is still untapped
3. Automated low-power design flow is up for grabs (Part II)

There is certainly no lack of competition in formal verification. The big three EDA public companies, Synopsys, Cadence, and Mentor Graphics, have all their own formal verification offering (Formality, Conformal, 0-in), and there are a number of startups, e.g., Jasper, Atrenta, Real Intent, OneSpin, Blue Pearl Software, to name a few. Formal verification products cover a wide range of applications: System Verilog Assertion (SVA) and property checking; RTL static check; equivalence checking (EC); some limited IP verification; clock-domain crossing (CDC) verification; and timing exception verification (false paths and multi-cycle paths).

Looking at the DAC submissions this year though, I am puzzled by the overwhelming number of papers focused on increasing simulation speed and coverage, as opposed to the handful of papers discussing formal techniques. And this year is not different from last year. And the year before last. Does that mean there is a lack of innovation in formal verification core techniques?

Improving simulation –higher coverage, less patterns, more automation— with formal techniques is a very active field, both in the academic and industrial world. Some inject faults in the RTL to separate the most discriminating patterns (e.g., Certess). Others use SAT and integer constraint solvers to reduce the number of patterns, or to automatically generate patterns for hard-to-cover code branches (e.g., NuSym). But success is all relative. Certess was quickly acquired last year, while NuSym is actively looking for a buyer. There are also semi-formal tools, mixing simulation and state exploration techniques (e.g., Magellan), but they a have limited usage.

What about the more fundamental formal verification technologies? The 80’s were dominated by the development of rigorous semantics models (e.g., multi-valued logic, Verilog and VHDL operational semantics for synthesis and simulation, temporal logics, and synchronous languages like Esterel and Lustre) and the introduction of BDDs. The 90’s saw EC tools spreading in the industry and the rise of model checking. The 00’s were all about SAT and model abstraction to push the capacity of EC and bring property checking to the end-user, as well as static code analysis, CDC, and timing verification. What are we going to see in this decade?

Verification has a lot of challenging problems, with incomplete or no solution at all. Here is my list:

• Merged arithmetic. There are robust methods to verify adders and multipliers of practically any size, but no one can verify merged arithmetics as small as 32-bits.
• Low power. This leads to complex properties capturing the correctness of sequential clock gating and power gating. The former is becoming more common, and there are techniques to address most of it (e.g., Calypto and Conformal). But the later is still waiting for a comprehensive and automated solution.
• RTL debugging. There are a number of static code checkers, but debugging is still very poor.
• HW/SW verification. Can we leverage deductive methods (predicate logic, HOL, rewriting system) to close the gap between software and RTL?
• Mixed signal (analog/digital) devices: this is a very young area of research, but it should see a lot of focus given the increasing ubiquity of mixed signal designs.

If formal verification core technology is to evolve, we will see some original solutions to the problems listed above. What do you think should be added to this list? And which techniques will evolve as the most promising?

Related posts:

1. The formal verification market is still untapped
2. Formal verification stalling, take two
3. Automated low-power design flow is up for grabs (Part I)

After about a year of seeing a desolated EDA landscape, littered with startups that could not find the money to survive to the next decade, or with promises that faltered as the semiconductor industry was hit hard with inventories it could not clear, the beginning of 2010 is suddenly looking brighter. Well, not as bright as I would like it to be, but there is definitely a sense of revival.

The semiconductor industry is announcing better-than-expected numbers for CY09Q4, and the recent Consumer Electronic Show (CES) led new expectations for exciting products that should be available within the year. How will this impact EDA? If impact there is, it will not be immediate, as many of its customers are still holding on their investments for the rest of the year, since most of their designs can be done with their current flows and tools. But, as pointed out by Richard Goering, CES showcased the hot products to come, and some will definitely require EDA tools to step up. Whether it is tablet PCs, ever more powerful mobile phones, 3D-TVs (over-hyped, if I may say so), USB 3.0, or wifi-enabled cars, there are plenty of avenues where mixed signals, low power, packaging, and high-capacity SoC design and verification tools can shine.

These are all familiar topics, but CES stressed the need for better, automated, and scalable solutions.

• Mixed signals will help Cadence –Synopsys does not have a credible solution there, and Magma is still too young in this market to push its Titan offering, regardless of its technical merits.
• Low power will be a leveled field, because there is no one-vendor comprehensive solution covering all its many facets; e.g., CPF/UPF support (Cadence and Synospys-Mentor-Magma respectively); RTL-level low power synthesis, which requires complex IP or/and manual architecturing; power-efficient clock tree synthesis, best done by Azuro and Mentor’s Olympus; and last but not least, low power verification, still led by Cadence’s Conformal.
• Early packaging estimation will be an interesting challenge –table PC and mobile phones require very thin, heat-dissipating, robust devices. Mentor and Cadence should capitalize on some of their technology and experience there.
• Large SoC design and verification is becoming more acute. Synospys and Mentor look positioned to make a move against an aging First Encounter-based Cadence solution.

It is still difficult to find money to finance new ventures or keep existing startups alive, so predicting what will come from startups is quite difficult for 2010. We will surely see whether Oasys, with its promise of 10-50x larger and faster synthesis, are for real. We will see whether ATopTech can separate itself from the increasingly commodity-like backend offering. We may see whether ESL or some flavor of C/C++-based hardware design environment can help addressing SoC challenges –for designing and verifying both the silicon and the software.

There is a window of opportunities driven by a recovering consumer electronic market, where EDA can demonstrate that innovation and responsiveness to the next technological challenge does pay off. Let the game begin.

Related posts:

1. Is FPGA a sustainable market for EDA?
2. DAC 47th digest: what you missed (even if you were there)
3. Why service companies will eat up EDA

Well, not millions after all. I have been writing mostly on EDA and related subjects, like outsourcing, software quality, and FPGA, covering both technical and business aspects; this is of interest to only a few tens of thousands of people. Most of these posts were featured in Design & Reuse, EDACafé, and CodeProject. Simply put, Design & Reuse has been for me the greatest portal to get an EDA audience to read my blog, right next to LinkedIn. Interestingly enough, quite a lot of traffic came from Yahoo finance because of two posts I had on Xilinx’ and Altera’s financial results. The fastest growing audience vector has been Twitter. I really started to use Twitter in September, and only now I can see Twitter to carry some significant interest from followers and retweets to my blog. It has been great to see comments and discussions unfolding around topics I discussed on this site.

One of my early blog, about why FPGA startups keep failing, captured a lot of interest. I had many comments on the blog, messages via LinkedIn, or direct feedback by email. But that post had an early start, so somehow I do not consider it as the most successful. The one that clearly hit a nerve is the post where I discussed EDA versus VLSI service companies. Two days after being published it racked up the number two spot of the most popular posts, and it triggered very interesting exchanges with a number of people in the industry.

After its inspection three months on a half ago, the twenty posts of my blog received just short of 10,000 views. I was glad to see one of my posts in the notable EDA blog postings for 2009 list of Richard Goering. EDA has been my passion for 20 years, still is, and it is exciting to establish new connections and opportunities via this blog.

But I have to admit that the traffic I draw to this blog is nothing compared to a handful of posts I wrote for TheNextWeb and Neowin. It was a great experience to write as a freelance and guest blogger, and I intend to pursue writing editorial, analysis, or opinion pieces for these high quality tech news sites.

I enjoy the interaction resulting from my writing about topics I care about. I hope that you, reader, enjoy it too. Let us meet again in 2010 on this site for more discussions.

I wish you a happy new year!

Related posts:

1. Why starting a blog in the first place?

It is good to learn that the customers of the EDA industry are doing better –if they do badly, EDA will do too. But will that seemingly economic improvement of the semiconductor industry translate into better days for EDA? Nothing is less certain. The recent quarterly reports of Synopsys, Mentor, Cadence, and Magma, although slightly above guidance, show a bleak outlook. Most of the book-to-bill ratios decreased, and they all carefully announcing a lean year ahead.

I recently ran into some acquaintance working for a leading semiconductor company (in the top 15), who told me that they are reaching out to services companies to get more values out of them. The numbers speak for themselves: they will put $12 millions down for an evaluation project that will encompass the full backend part of the design cycle –about 8 months project. That is only for an evaluation! When was the last time any EDA company was given that amount of cash for a real-life trial?

More numbers? Let us only look at the VLSI service companies in India, i.e., in no specific order: HCL Technologies, KPIT Cummins Infosystems Ltd, MindTree Ltd, Sasken Communication Technologies, Tata Consultancy Services, Wipro Technologies. According to the India Semiconductor Association, VLSI design service revenues in India could hit $1.13 billion in 2009, while hardware and board design could reach $560 million and embedded design and services about $7.29 billion. Yes, that’s nearly $9 billion overall, nearly twice the EDA market, and China is not even in the picture yet. Despite the dramatic downturn in 2009, some of these services companies did quite well, and most expect an uptick with a recovery in the semi industry next year.

The truth is that EDA companies have been providing software solutions that are more and more seen as commodities. The license renewal rate is dropping and its volume is decreasing.  In a flat, if not slowly shrinking market, the EDA firms have to eat their competitors’ share if they want to grow or just survive. They drop their prices and fork free AE support to sweet the deal for the customer. The vast majority of the designs can be done with last year’s generation suite, thus there is no urgency to buy new design tools. Then semiconductor companies might indeed be better off with a dedicated service company, which provides hands-on design expertise, and will be judged on results, i.e., the final tapeout. This is a win-win situation: the customer can fully rely on the service company, and since this business model commands a much higher fee than for a software license, the service company can expand and further invest to be an intimate part of their customers’ flows.

EDA has better look around and see what is happening. Semiconductors companies will more and more rely on service companies, tailored to their needs. Chip design and verification looks more and more like an IP assembly that requires an expertise that EDA tools do no longer deliver. The value-added is in that expertise, not in the tools that are becoming more and more push-process.

It is true that VLSI service companies buy tools to EDA companies, but the service companies factorize the license usage between several customers, which means that overall, less licenses are needed. Today, TCS can easily rent any EDA tool from the big 3 by the week or by the month. Imagine tomorrow Synopsys, Cadence, and Mentor dealing only with the top 6 hardware design service companies, themselves servicing the top 20-30 in the semi industry: EDA will loose a lot of leverage in the sale negotiation process. If Magma ends up as a cheap provider of IC implementation solutions, all developed in India, it will lower the bar even more.

EDA has to evolve quickly if it does not want to be sidelined as just an enabler. The EDA industry must be part of the design expertise, and work closely with its customers, even if it means its solution is no longer generic. And yes, as I said in the past, the value-added is in the system-level software, and this is where resides the growth of hardware designs. So the EDA industry must go into chip software design and verification if it wants to be relevant in five years from now.

Related posts:

1. What EDA needs to change for 2020 success?
2. Software outsourcing, a necessary evil
3. How can Xilinx improve its bottom line

Paul rightly emphasized three trends. The first one is well know: the continuously rising cost of IC designs, about $50M for today’s 45nm node. The second trend is that the fastest growing part of the design cost is software –more than half of the overall cost, Paul even claiming close to 2/3 of the overall cost. The third trend is an increasingly fragmented consumer market: the number of end products goes into the 10’s of billions, but these products are declined in many more different kinds, which means that most of them are shipping in smaller individual volumes.

Source: Morgan Stanley, Economy + Internet Trends, Web 2.0 Summit, San Francisco, Oct 2009.

This is bad news for EDA as we know it: the rising cost of design can no longer be justified if the number of units does not grow fast enough (a $50M chip starts to make sense only if it is produced for 250M units and more). Also EDA has been slow to climb up the food chain and proposes solutions for software design, which dominates the overall chip design cost.

Rising IC design cost and smaller number of units is the call for FPGA to growth even faster. Mobile applications require FPGA to do much better in terms of power consumption, but this is a hot topic (no pun intended) drawing a lot of attention and investment, and some competitive solution will emerge in the next few years. So EDA, which makes its bread and butter on IC design, should better re-align its growth strategy on software, embedded systems, HW/SW co-design, and verification. Else EDA will continue to shrink to only service the few that can still afford chip design.

The end product, as a SoC, is a puzzle where the designer mostly assembles existing cores and IPs, and decides of the tradeoff between the software and hardware parts, based on flexibility and cost factors.

I see two strong needs that EDA could build its growth on. One is functional validation of the whole system –software plus hardware. EDA has started to address the issue, even though it is still short of proposing a scalable and automated environment. To functional validation, I would also add functional flexibility: how much of the behavior can be upgraded thanks to the software part? The other need is a design navigator that would estimate the speed, area, power consumption, and cost of a SoC by exploring alternatives between cores (ARM, MIPS, etc), IPs, FPGA, and software.

Last but not least, the eternal question of an EDA serving a $250B semiconductor industry, but making less than $5B. The time-based license model has only served the interests of the semiconductor companies, to the expenses of R&D investment in EDA. Claiming a lack of innovation in the EDA industry is sometimes fair, but EDA should also innovate in business solutions instead of cannibalizing itself by cutting costs to only survive another quarter. The semiconductor industry needs a healthy EDA if it wants to address the system-level design challenges of the next 10 years. Unless, of course, a new player coming from the software world with the experience of scalable systems signs the death of the EDA industry as we know it.

Related posts:

1. The formal verification market is still untapped
2. Why service companies will eat up EDA
3. Is FPGA a sustainable market for EDA?