It is good to learn that the customers of the EDA industry are doing better –if they do badly, EDA will do too. But will that seemingly economic improvement of the semiconductor industry translate into better days for EDA? Nothing is less certain. The recent quarterly reports of Synopsys, Mentor, Cadence, and Magma, although slightly above guidance, show a bleak outlook. Most of the book-to-bill ratios decreased, and they all carefully announcing a lean year ahead.

I recently ran into some acquaintance working for a leading semiconductor company (in the top 15), who told me that they are reaching out to services companies to get more values out of them. The numbers speak for themselves: they will put $12 millions down for an evaluation project that will encompass the full backend part of the design cycle –about 8 months project. That is only for an evaluation! When was the last time any EDA company was given that amount of cash for a real-life trial?

More numbers? Let us only look at the VLSI service companies in India, i.e., in no specific order: HCL Technologies, KPIT Cummins Infosystems Ltd, MindTree Ltd, Sasken Communication Technologies, Tata Consultancy Services, Wipro Technologies. According to the India Semiconductor Association, VLSI design service revenues in India could hit $1.13 billion in 2009, while hardware and board design could reach $560 million and embedded design and services about $7.29 billion. Yes, that’s nearly $9 billion overall, nearly twice the EDA market, and China is not even in the picture yet. Despite the dramatic downturn in 2009, some of these services companies did quite well, and most expect an uptick with a recovery in the semi industry next year.

The truth is that EDA companies have been providing software solutions that are more and more seen as commodities. The license renewal rate is dropping and its volume is decreasing.  In a flat, if not slowly shrinking market, the EDA firms have to eat their competitors’ share if they want to grow or just survive. They drop their prices and fork free AE support to sweet the deal for the customer. The vast majority of the designs can be done with last year’s generation suite, thus there is no urgency to buy new design tools. Then semiconductor companies might indeed be better off with a dedicated service company, which provides hands-on design expertise, and will be judged on results, i.e., the final tapeout. This is a win-win situation: the customer can fully rely on the service company, and since this business model commands a much higher fee than for a software license, the service company can expand and further invest to be an intimate part of their customers’ flows.

EDA has better look around and see what is happening. Semiconductors companies will more and more rely on service companies, tailored to their needs. Chip design and verification looks more and more like an IP assembly that requires an expertise that EDA tools do no longer deliver. The value-added is in that expertise, not in the tools that are becoming more and more push-process.

It is true that VLSI service companies buy tools to EDA companies, but the service companies factorize the license usage between several customers, which means that overall, less licenses are needed. Today, TCS can easily rent any EDA tool from the big 3 by the week or by the month. Imagine tomorrow Synopsys, Cadence, and Mentor dealing only with the top 6 hardware design service companies, themselves servicing the top 20-30 in the semi industry: EDA will loose a lot of leverage in the sale negotiation process. If Magma ends up as a cheap provider of IC implementation solutions, all developed in India, it will lower the bar even more.

EDA has to evolve quickly if it does not want to be sidelined as just an enabler. The EDA industry must be part of the design expertise, and work closely with its customers, even if it means its solution is no longer generic. And yes, as I said in the past, the value-added is in the system-level software, and this is where resides the growth of hardware designs. So the EDA industry must go into chip software design and verification if it wants to be relevant in five years from now.

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Paul rightly emphasized three trends. The first one is well know: the continuously rising cost of IC designs, about $50M for today’s 45nm node. The second trend is that the fastest growing part of the design cost is software –more than half of the overall cost, Paul even claiming close to 2/3 of the overall cost. The third trend is an increasingly fragmented consumer market: the number of end products goes into the 10’s of billions, but these products are declined in many more different kinds, which means that most of them are shipping in smaller individual volumes.

Source: Morgan Stanley, Economy + Internet Trends, Web 2.0 Summit, San Francisco, Oct 2009.

This is bad news for EDA as we know it: the rising cost of design can no longer be justified if the number of units does not grow fast enough (a $50M chip starts to make sense only if it is produced for 250M units and more). Also EDA has been slow to climb up the food chain and proposes solutions for software design, which dominates the overall chip design cost.

Rising IC design cost and smaller number of units is the call for FPGA to growth even faster. Mobile applications require FPGA to do much better in terms of power consumption, but this is a hot topic (no pun intended) drawing a lot of attention and investment, and some competitive solution will emerge in the next few years. So EDA, which makes its bread and butter on IC design, should better re-align its growth strategy on software, embedded systems, HW/SW co-design, and verification. Else EDA will continue to shrink to only service the few that can still afford chip design.

The end product, as a SoC, is a puzzle where the designer mostly assembles existing cores and IPs, and decides of the tradeoff between the software and hardware parts, based on flexibility and cost factors.

I see two strong needs that EDA could build its growth on. One is functional validation of the whole system –software plus hardware. EDA has started to address the issue, even though it is still short of proposing a scalable and automated environment. To functional validation, I would also add functional flexibility: how much of the behavior can be upgraded thanks to the software part? The other need is a design navigator that would estimate the speed, area, power consumption, and cost of a SoC by exploring alternatives between cores (ARM, MIPS, etc), IPs, FPGA, and software.

Last but not least, the eternal question of an EDA serving a $250B semiconductor industry, but making less than $5B. The time-based license model has only served the interests of the semiconductor companies, to the expenses of R&D investment in EDA. Claiming a lack of innovation in the EDA industry is sometimes fair, but EDA should also innovate in business solutions instead of cannibalizing itself by cutting costs to only survive another quarter. The semiconductor industry needs a healthy EDA if it wants to address the system-level design challenges of the next 10 years. Unless, of course, a new player coming from the software world with the experience of scalable systems signs the death of the EDA industry as we know it.

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Getting actual figures about the size of the functional verification market proves to be elusive because of the way the products are tied to synthesis license deals, and because of the lack of independent analysts in EDA. Still, the simulation and emulation market of digital systems can be estimated to be at least five times larger than today’s formal verification market. But simulation can only take you so far, so one wonders why formal verification does not have a larger share. Is it because the technology is limited, or because the market is not ready?

Equivalence checking

Equivalence checking (EC) consists of verifying that a netlist implements the behavior specified by a RTL description, or that two netlists are equivalent. Historically, EC is the first industrial formal verification tool brought to the ASIC world. Cadence’s Conformal is still the reference (about 60% of the market), with Synopsys’ Formality coming second.

EC’s technology is very mature, but this does not mean no further progress is necessary. Flip-flop matching, the primarily step that consists of determining the pairs of flip-flops that need to be compared, is expected to be done quickly and automatically, with no manual guidance. Datapath verification remains a major challenge, and proving the correctness of merged arithmetic automatically is still an open problem. Last but not least, debugging is a very complicated task. Incremental verification and rectification techniques can be quite useful to help pinpointing the functional issue.

Model checking and property verification

Model checking and property verification are still a fraction of the formal verification market, with many players on the field. There are two obstacles for a larger usage of the approach. The first one is that it can be complicated to write a FSM or property that captures a particular behavior. SVA (System Verilog Assertions), OVL (Open Verification Library), and PSL (Property Specification Language) help in that regard, but they need to be more systematically used in the design community. The second obstacle is that model checking techniques can only solve relatively small problem instances. This is why some go with hybrid verification techniques (read: may be incomplete), like Magellan or 0-in, while other stick with complete formal methods, like Jasper and OneSpin.

Because writing properties can be so complicated, specialized branches grew to address specific needs, as shown below.

• IP verification. With SoCs using IPs from many different sources, verifying the compliance of these IPs with respect to standard interfaces (e.g., PCI or USB) in the context of the application is crucial.  Conformal, with its verification IP portfolio, is in a good position to address the problem. Also OneSpin is known to have interesting technology in that space, even though they are not pushing it at the moment.
• Timing verification. Incorrect timing constraints can lead to missing a target clock cycle, or worse, to a chip failure. Verifying timing exceptions (false paths and multi-cycle paths), as well as CDC (Clock-Domain Crossing), has become a center of attention. It is still unclear how big the market is. However several discussions with IC design companies led me to believe that verifying a set of timing exceptions (usually in the order of 10,000 SDC constraints) save one month work of an engineer. Automation and speed are keys here. Atrenta, Real Intent, and 0-in propose interesting solutions in that space.
• Power verification. When doing power gating, one needs to verify that the application is powered back up properly. Integration with UPF or CPF provides the required automation. Conformal and CPF have an edge in that field.
• Sequential clock gating verification. Traditional (combinatorial) clock gating is well supported by EC tools. Sequential clock gating exploits sequential dependencies to derive additional gating conditions, which can be used to save more dynamic power. It has been made popular by Calypto –Envis is also proposing a similar technique at the netlist level. Sequential clock gating correctness cannot be expressed easily with SVA or OVL without making the verification task extremely complex, which explained why specialized verification techniques have been developed.

Where formal verification will grow

Formal verification is no longer limited to ASICs: complex systems –SoC, FPGA, and HW/SW co-design— will benefit dramatically from better formal verification techniques if they are deployed adequately.

With the ever-growing size of FPGAs (Altera’s Stratix IV packs 820k logic elements, and Xilinx’ Virtex-6 has up to 750k logic cells), it is clear that simulation will no longer be sufficient to validate the correctness of programmable logic devices. The need for FPGA EC is real, and this requires complete automation and full support for retiming –OneSpin’s 360 EC FPGA has shown some competitive solution in that space. Also note that IP verification and timing verification apply to the FPGA designs too. The real question is whether FPGA designers are willing to pay for formal verification tools.

IP verification, and verifying the correctness of a SoC using IPs, is certainly a very strong driver for more sophisticated formal verification solutions. Power verification will become part of the ASIC design flow, as EC is part of the synthesis flow. Timing verification is still looking for its footing in the design flow –one question is the debug environment, which is still relatively limited, e.g., to showing waveforms.

Looking forward, formal verification techniques can be used (and have been used) in other fields than circuit design. Any critical digital system can benefit from formal verification techniques –transportation, medical equipments, security and privacy applications. The automotive industry is one of the most obvious targets. Cars are ubiquitous, they contains more and more electronics (representing about 30% of the end price today), and a functional bug can have very costly consequences. Cars rely on digital systems for anything from optimizing their engine’s efficiency to navigation systems, entertainment, and on-board diagnosis. Soon the intra-vehicle, vehicle-to-vehicle, and vehicle-to-roadside networking will fuel innovative products, driving the needs for fast development and the highest possible level of correctness. The EDA industry is taking notice, and Mentor has certainly taken the lead there. Whether they provide the adequate functional verification framework is another matter.

Formal verification will extend its reach by addressing the hard problems of EC (datapath verification, and retiming for FPGA), by being seamlessly integrated in the synthesis flow (power and timing exception verification), and by providing practical solutions to IP and hybrid HW/SW design verification.

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I will focus on three items necessary for power gating: (1) the FSM that controls the sleep and wake-up sequences; (2) the retention flops used to restore the state of the device when it is awakened; and (3) the correctness of the power gating implementation. Items (1) and (2) are manually done via UPF/CPF directives and FSM hand-coding. Item (3) is carried out with customer-specific methods, even though the use of CPF together with Conformal produces a more solid verification flow.

Sleep/wake-up protocol synthesis

Items (1) and (2) must really be considered together to answer the following question: how to implement a sleep and wake-up sequences that use retention flip-flops to resume the device’s state? It is clear that answers to that question are different tradeoffs between the number of retention flops and the length of the sequences. The more retention flops, the shorter the sequences are, but the higher the price in terms of area and residual leakage power. In essence, one would like to be able to explore the possible tradeoffs and pick the best compromise, depending on the application. Also from the designer point of view, one should not have to manually decide which flip-flops must be shadowed, nor one should have to hand-code the FSMs for the sleep and wake-up sequences.

Instead, one should be able to synthesize the retention flip-flops and the sleep and wake-up FSMs directly from a power state table –what I call sleep/wake-up protocol synthesis. I would propose an extension of the power state table so that transitions can also be labeled with constraints: an upper bound on the sequence length (in terms of number of clock cycles or milliseconds), and an upper bound on the area taken by the retention flops (actual area or as a percentage of the element area). This way the designer can concentrate on the power management strategy and explore different tradeoffs, instead of having to figure out the implementation itself.

Sleep/wake-up protocol synthesis is no small task. I would look into information relevance and functional dependency analysis to derive a candidate set of retention flops. Compression and encoding methods can then be used to reduce this set. The final FSM synthesis would implement the decoder. Looking into techniques coming from DFT, simulation, and formal verification could prove very helpful.

Sleep/wake-up protocol verification

Item (3) is verifying the correctness of the power gating implementation. There are two aspects here. One is purely physical, and consists of checking that level shifters, isolation cells, and power switches have been properly inserted. The insertion of these cells can be automated, and verifying that their insertion obey basic physical rules in not a problem (this is supported for both UPF and CPF).

The main issue is to verify the functional correctness of the sleep/wake-up sequences, namely that the device meets some operational expectation once re-activated (e.g., the pre-sleep state is fully restored). Intensive simulation will give some coverage, but cannot be exhaustive in general. Sequential formal verification or property checker can then be used for a proof of correctness. For instance the property would go something like “if the device goes to sleep and then is re-activated, its state is fully restored to its pre-sleep state in less than one second”. To be manageable, such a property must be broken down in smaller or more abstract expressions. The same synthesis system that takes care of items (1) and (2) should generate the properties that a 3^rd party property checker can independently verify to guarantee the correctness of the sleep/wake-up protocol. This is no different than a RTL synthesis tool giving hints to an equivalence checker to simplify the proof.

Conclusion

Given the complexity of today’s sleep/wake-up protocol design and verification, it is somewhat surprising that no EDA tool is really tackling the problem today. Is it because of user unawareness, or because of the size of the challenge? Regardless of the reason, the first company to offer sleep/wake up protocol synthesis and verification will make a major impact in the low power design community.

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For mobile products, leakage power (the power consumed when the device is on but idle) has become a dominant factor, as opposed to dynamic power (the power resulting from the actual activity of the device, e.g., during a call for a cell phone). In that context, power gating is a key for extended battery life. Under some condition (e.g., the “on/off” button is pressed, or the device has been unused for some time), the device goes to sleep: it powers down most of its elements and preserves enough information to restore the state it was in before going to sleep. Under another condition (e.g., the “on/off” button is pressed again), the device powers back up and resumes its course as it was right before going to sleep.

UPF (Unified Power Format, endorsed by Synopsys, Mentor, and Magma) has been introduced to describe the power supply distribution and its control. With UPF one can specify power domains (a set of design elements that share a power supply), and a power state table that captures the transitions between the power domains. For instance it is used to describe under which conditions the device goes to sleep, under which conditions it must be powered back up, and what happens whenever the device transitions between these modes. UPF allows the designer to specify retention flops, level shifters, and isolation cells, all necessary items for multiple voltage designs and power gating. CPF, promoted by Cadence, is another format that is used to describe similar power management schemes.

Low power has been a subject of attention from chip designers and EDA for more than 10 years. Indeed, a lot of improvement has been done. New techniques have been introduced, and most are now common practices and relatively well automated –clock gating, multiple Vt cells, multiple voltages.

Despite these progresses, low power-centric design flows remain a very labor intensive process. Even if UPF/CPF can be used to describe transitions between different power modes, it is up to the designer to manually write the controller (as a FSM) that implements the transitions, and it is up to the designer to determine which information must be preserved (the retention flops) in order to resume the application to its pre-sleep state.

Also low-power designs create new challenges for functional verification. For instance, after going to sleep, the device must be able to resume without loss of information. Since the sleep and power-back-up sequences take several clock cycles, simple equivalence checking is not sufficient. Sequential verification or intensive simulation is needed. Cadence did a relatively good job in tying CPF to its Formal Verification solution (Conformal), Mentor and Synopsys have some reasonable flow for UPF, but verifying the correctness of a power state table FSM is still a very manual and error-prone process.

EDA stands for bringing automation to design flows, and low power design could use some help. In Part II, I will show how some parts of the low power design flow can be automated.

Glossary

Sleep mode: the power state a device is in when it is not actively used by the user. In that state most of the device is shut down, but is ready to wake up when the user needs it.

Active mode: the power state a device is when it is fully active (e.g., making a call with a cell phone).

Power domain: a set of design elements that share a power supply. Power domain is also used to denote the power supply itself.

Power state table: a table that describes the transitions between power domains. Transitions are annotated with logical expressions under which they are triggered.

Retention flop: an always-on flop that shadows the state of a flop. It retains its logic state even when the primary power supply to the cell is shut off. It is used to restore the state of a device when it is powered back up.

Level shifter: cell used to allow a signal to pass from one power domain to another.

Isolation Cell: cell used to isolate a device element from its neighbors when it is powered down.

Clock gating: power-saving technique that consists of blocking the clock signal leading to flops so that flops cannot change their state. Since their states are fixed, the downstream logic will not toggle, which saves dynamic power.

Power gating: power-saving technique that consists of shutting down the power supply to a device component, so that its power consumption is zero.

Multiple Vt: multiple voltage threshold cells. A cell speed depends on its voltage threshold. The lower its voltage threshold, the faster the cell is, but the higher its leakage power. High Vt cells are used for non-timing critical parts of the circuit, while low Vt cells are used for critical paths only, so that the overall leakage power is reduced.

Multiple voltages, Voltage islands, MVDD: a component of a circuit can operate under several voltages, or components can have different operational voltage. The higher the voltage, the faster the component is, the higher its leakage and dynamic power.

Dynamic power: the power dissipated by a circuit due to its cells switching from one state to the next. It is proportional to Vdd²tr, where Vdd is the voltage supply of the cell, and tr is its transition rate (or toggle rate) per second.

Leakage power, static power: the power dissipated due to the leakage current passing through transistors. Practically it is the power dissipated when the cell does not toggle. It is proportional to Vdd exp(- Vt / T), where Vdd is the voltage supply of the cell, Vt is its voltage threshold, and T the temperature.

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