Olivier Coudert on December 11th, 2009

Over the past week we heard good news from Xilinx and Altera, both raising their revenue targets for Q4CY09 (Q3FY10 and Q4FY09 respectively). Both of the FPGA giants are doing fine, and are poised to grow twice as fast as the semiconductor industry. The semiconductors companies are doing well too, with TI upping its Q4CY09 […]

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Olivier Coudert on November 6th, 2009

ICCAD’09 was a fairly good vintage. It started Monday morning with an excellent keynote from Hamid Pirahesh about cloud computing. The same day in the afternoon, a more EDA-focused discussion was initiated by Jim Hogan and Paul McLellan (slides can be found here), asking the question “What EDA needs to change for 2020 success?” Paul […]

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Olivier Coudert on October 19th, 2009

Functional verification is a major bottleneck in the chip design cycle. Any misstep in closing the functional correctness of a digital system costs millions of dollars in redesign, additional testing, and silicon respins. One can argue at length about its actual cost, but people in the industry usually agree that functional verification takes between 40 […]

Continue reading about The formal verification market is still untapped

Olivier Coudert on October 6th, 2009

A previous post showed a very-high level view of low power design with UPF/CPF. Power gating, a must-do for mobile products, is still a very manual process, and verifying the correctness of its implementation is a very challenging task. In this follow-up post, I single out some aspects of the power-gating flow, and I hint […]

Continue reading about Automated low-power design flow is up for grabs (Part II)

Olivier Coudert on October 5th, 2009

Low power is becoming more and more critical as the number of mobile and wireless applications is increasing. Battery life is a feature that can make the difference between a success and a flop. Remember the first version of the iPhone? All praised the touch screen interface, but so many criticized its poor battery life. […]

Continue reading about Automated low-power design flow is up for grabs (Part I)