The dominant factor in classical FPGA architecture is the interconnect: most of the die area is taken by the wires and the interconnect switches and muxes. If you can somehow reduce the area dedicated to interconnect, you can augment the logic density and lessen the cost of the device. Tabula and Tier Logic pitch a 3D architecture to address the interconnect bottleneck, albeit in very different flavors.

Tabula innovative design is based on its ability to reconfigure itself, up to 8 times with a clock running at 1.6GHz. At each cycle a cell can change its functionality, its latch configuration, and its interconnect. The time-multiplexing increases the amount of logic that can be fit on the same area. It is like having 8 layers (or “folds”) of cells stacked on top of each other along a time axis, with very short connection between cells at the same (x,y) coordinate but in two adjacent folds. At each cycle one jumps to the next fold and feeds the new configured logic with the results of the previous fold. Tabula claims they increase the logic density by 2.5x compared to classical FPGA architectures.

Tier Logic’s design idea is to place the SRAM cells that configure the interconnect muxes on top of the routing layers, instead of having them distributed throughout the logic die area. Doing so leaves more room for logic cells, increasing the cell density by about 50% according to the company. The design flow will not throw anybody off: it uses Mentor’s Precision for synthesis, and is followed by Tier Logic’s mapping and P&R.

A big plus touted by Tier Logic is the ability of moving painlessly from their device to an ASIC. Simply replace the interconnect configuration SRAM cells at the top with metal, and voila, you obtain an ASIC with no change in timing. This is a simple, predictable process: it takes about 4 weeks to go from the SRAM configuration to a top-layer mask, and you do not need to go through a timing closure flow again, which means a non-recurring engineering cost of about $50k. This is a real bargain when you consider that moving from FPGA to ASIC usually requires a redesign that can take as long as 9 months.

So who of Tabula and Tier Logic is best positioned to challenge the duopoly Xilinx/Altera?

Tabula made it clear that they are aiming at the high-end of the FPGA market. There are a number of FPGA startups that targeted the same niche, and none survived. One reason is that it is easy for Xilinx and Altera to increase the size of their device, by simply moving to the next technology node. Tabula’s design is innovative and pushes the limits, but how far is too far? It is unclear whether the company can deliver the design tools to match their device’s challenges –they went through a complete reset a few years ago, replacing the whole software team. Verifying a device that can reconfigure itself 8 times in a loop may be another challenging problem. Increased density is obtained by continuous reconfiguration, which means extra power consumption: is it still an acceptable tradeoff? Last but not least, with 100+ people in the US, it is a well-known fact in the Silicon Valley that Tabula burns cash fast, and their funding of $106 millions so far is about to come short.

Tier Logic’s FPGA can reduce the cost of the device for the same density. But their compelling value proposition is really their FPGA to ASIC translation. This is what Altera’s HardCopy was supposed to be, a seamless and risk-free migration from FPGA to ASIC. For anybody that wants to design an application and then migrate to a low/medium volume ASIC production, this could be the most cost efficient solution. I do not know the inside story regarding the financial aspect, but their business proposal looks more solid.

So who do you think has a chance here? Let’s meet again in 3-4 quarters and see how the two companies are doing.

Related posts:

1. RIP Tier Logic
2. Why FPGA startups keep failing
3. RIP Abound Logic

Comparing the yearly fiscal exercises directly would be biased (Xilinx’ fiscal year end on March 31^st, and Altera’s fiscal year on Dec 31^st). Instead we can look at a quarter by quarter comparison, even though that can be too low a level. Better is to look for ttm (trailing twelve months) comparison to smooth out the local variations.

Source: Yahoo! Finance. All figures in thousands.

One can see that Altera’s operating margin is overall better. Also in their respective Q3’09 revenue reports, Xilinx expects its Q4’09 gross margin to improve to 62-63%, and Altera sees his to be 67-68%.  So a 3-4% operating margin gap will remain, which is significant.

On the other hand, Xilinx quotes 3145 full time employees, and Altera 2760. This means that a Xilinx employee brings back revenue about 26% higher than an Altera employee! So it all boils down to the question: how can Xilinx be more cost efficient?

One of the differences is the way software is developed. Altera’s software is mostly done in their technology center of Penang, Malaysia, with a very small core technology group in Toronto, Canada. Xilinx’s software team is mostly in the US, and only 5% of the team is in their R&D facilities in Hyderabad, India. A back-of-the-envelop calculation shows that if Xilinx had the same software team but with a US/India ratio 1/3-2/3, which is a healthy ratio for a company that can leverage its India facility, Xilinx would improve its operating margin by one point.

If you extend the same reasoning to whole R&D –not only software–, then it is clear that Xilinx can get the upper hand. Looking at the R&D job listings, it is also clear that Xilinx is moving into that direction. The question then is whether Xilinx has the structure and the drive to achieve such a transformation successfully.

Related posts:

1. What to read in Xilinx’ and Altera’s third quarter results
2. Who should worry about Xilinx and Oasys partnership?
3. Software outsourcing, a necessary evil

Source: Xilinx and Altera financial reports, and Yahoo! Finance

Xilinx’ quarterly income of $64M (0.23$/share) beats Wall Street’s expectation of 0.19$/share. Altera’s quarterly income of $56.7M (0.19$/share) meets Wall Street’s expectation. Both companies expect a 6-10% revenue increase for Q4’09 from previous quarter. Xilinx expects its Q4’09 gross margin to improve to 62-63%, and Altera sees his to be 67-68%.

Both companies are benefiting equally of an improving economy. Altera is seeing a large part of its revenue coming from new products (60% for Q3’09), as opposed to Xilinx (31% in Q3’09).

I would give a slight edge to Altera, given its recent offer of high-performance new devices, and its operation margin consistently ahead of Xilinx’. One day Xilinx should be able to close the 3-4% operation margin gap it has with Altera, but until then it will not be as efficient and dynamic as Altera. I will discuss in another post how Xilinx can close this gap.

Related posts:

1. How can Xilinx improve its bottom line
2. Who should worry about Xilinx and Oasys partnership?