Online publications can be found here.

  1. O. Coudert, “Model Checking in the Cloud”, slides available, in FMCAD’12, Oct. 2012.
  2. O. Coudert, “Chip Design and Cloud Computing: a Perfect Storm“, slides available, in Cloud Slam’12, May 2012.
  3. O. Coudert, “An Efficient Algorithm to Verify Generalized False Paths“, in DAC’10, June 2010.
  4. O. Coudert, “Rapid High Capacity Prototyping and Physical Synthesis“, in SAME’2002, Oct. 2002.
  5. O. Coudert, “Physical Implementation: Challenges and Implementation“, in EE Times Asia, June 3, 2002.
  6. O. Coudert, “Timing and Design Closure in Physical Design Flows“, in Proc. of ISQED’2002, CA, March 2002.
  7. O. Coudert, “Logical and Physical Design: A Flow Perspective“, Logic Synthesis and Verification, S. Hassoun & T. Sasao Editors, Kluwer Academic Publishers, Chapter 1, pp. 1–27, 2001.
  8. O. Coudert, T. Sasao, “Two-Level Logic Minimization“, Logic Synthesis and Verification, S. Hassoun & T. Sasao Editors, Kluwer Academic Publishers, Chapter 1, pp. 167–196, 2001.
  9. O. Coudert, J. Cong, S. Malik, M. Sarrafzadeh, “Incremental CAD“, in Proc. of ICCAD’2000, CA, Nov. 2000.
  10. M. Koegst, O. Coudert, S. Ruelke, “A Generalized Constraint-Driven State Encoding Strategy”, in Proc. of EUROMICRO’99, Sept. 1999.
  11. O. Coudert, “Selection Graph Coloring: Application to Constrained Encoding”, submitted to DAC’99, Oct 1998.
  12. B. Yang, R. E. Bryant, D. R. O’Hallaron, A. Biere, O. Coudert, G. Janssen, R. K. Ranjan, F. Somenzi, “A Performance Study of BDD-Based Model Checking“, in Proc. of FMCAD’98, Palo Alto CA, Oct. 1998.
  13. O. Coudert, “Solving Dichotomy-based Constrained Encoding With Twin Graph Coloring“, in Proc. of IWLS’98, Lake Tahoe CA, June 1998.
  14. O. Coudert, “A New Paradigm for Dichotomy-based Constrained Encoding“, in Proc. of Design, Automation and Test in Europe (DATE), Paris, France, Feb. 1998.
  15. O. Coudert, “An Exact Algorithm to Color Real-Life Graphs“, submitted (March 1997) to IEEE Trans. on Computers.
  16. O. Coudert, “Gate Sizing for Constrained Delay/Power/Area Optimization“, in IEEE Trans. on VLSI Systems, Special Issue on Low Power Electronics and Design, 5-4, pp. 465–472, Dec. 1997.
  17. O. Coudert, “Exact Coloring of Real-Life Graphs is Easy“, in Proc. of 34th DAC, Anaheim, CA, June 1997.
  18. O. Coudert, “Coloring Real-Life Graphs“, in Proc. of IWLS’97, Lake Tahoe CA, May 1997.
  19. O. Coudert, “Solving Graph Optimization Problems with ZBDDs“, in Proc. of ED&TC’97, Paris, France, March 1997.
  20. O. Coudert, C.-J. Richard Shi, “Exact Dichotomy-based Constrained Encoding“, in Proc. of ICCD’96, Austin TX, Oct. 1996.
  21. O. Coudert, R. Haddad, K. Keutzer, “What is the state of the art in commercial CAD tools for low power?“, in Proc. of 1996 Int’l Symposium on Low Power Electronics and Design, Monterey CA, Aug. 1996.
  22. O. Coudert, R. Haddad, “Integrated Resynthesis for Low Power“, in Proc. of 1996 Int’l Symposium on Low Power Electronics and Design, Monterey CA, Aug. 1996.
  23. O. Coudert, “On Solving Covering Problems“, in Proc. of 33rd DAC, Las Vegas, June 1996. Best paper award
  24. O. Coudert, R. Haddad, S. Manne, “New Algorithms for Gate Sizing: A Comparative Study“, in Proc. of 33rd DAC, Las Vegas, June 1996.
  25. O. Coudert, C.-J. Richard Shi, “Exact Multi-Layer Topological Planar Routing“, in Proc. of CICC’96, pp. 179-182, San Diego CA, May 1996.
  26. O. Coudert, “Gate Sizing: a General Purpose Optimization Approach“, in Proc. of ED&TC’96, pp 214-218, Paris, France, March 1996. Best paper award
  27. O. Coudert, J. C. Madre, “New Ideas for Solving Covering Problems“, in Proc. of 32nd DAC, San Francisco CA, June 1995.
  28. O. Coudert, “On Solving Binate Covering Problems“, Int’l Workshop on Logic Synthesis, Lake Tahoe CA, May 1995.
  29. O. Coudert, “Doing Two-Level Logic Minimization 100 Times Faster“, in Proc. of Symposium on Discrete Algorithms (SODA), pp. 112-121, San Francisco CA, Jan. 1995.
  30. O. Coudert, J. C. Madre, “The Implicit Set Paradigm: A New Approach to Finite State System Verification“, in Formal Methods in System Design Journal, E. M. Clarke Editor, Kluwer Academic Publishers, Vol. 6, pp. 133-145, 1995.
  31. O. Coudert, “Two-Level Logic Minimization: An Overview“, Integration Vol. 17, No. 2, pp. 97-140, Oct. 1994.
  32. O. Coudert, J. C. Madre, “METAPRIME, an Interactive Fault Tree Analyser“, in IEEE Trans. on Reliability, 43-1,
    pp. 121-127, March 1994.
  33. O. Coudert, J. C. Madre, “Une Approche Intentionnelle du Calcul des Implicants Premiers et Essentiels des Fonctions Booléennes”, Informatique Théorique et Applications (ITA) Vol. 28(2): 125-149 (1994)
  34. J. C. Madre, O. Coudert, H. Fraisse, “Application of a New Logically Complete ATMS to Digraph and Network Connectivity Analysis“, in Proc. of Annual Reliability and Maintainability Symposium, Anaheim CA, USA, Jan. 1994.
  35. O. Coudert, J. C. Madre, H. Fraisse, “New Qualitative Analysis Strategies in METAPRIME“, in Proc. of Annual Reliability and Maintainability Symposium, Anaheim CA, USA, Jan. 1994.
  36. O. Coudert, J. C. Madre, H. Fraisse, H. Touati, “Implicit Prime Cover Computation: An Overview“, in Proc. of SASIMI’93 (Synthesis And SImulation Meeting and Int’l Interchange), Nara, Japan, Oct. 1993.
  37. O. Coudert, J. C. Madre, H. Fraisse, “A New Viewpoint on Two-Level Logic Minimization“, in Proc. of 30th DAC, Dallas TX, USA, June 1993. Best paper award candidate
  38. O. Coudert, J. C. Madre, “Towards a Symbolic Logic Minimization Algorithm“, in Proc. of the VLSI Design’93, Bombay, India, Jan. 1993.
  39. O. Coudert, J. C. Madre, “Fault Tree Analysis: 10^20 Prime Implicants and Beyond“, in Proc. of the Annual Reliability and Maintainability Symposium, Atlanta NC, USA, Jan. 1993.
  40. O. Coudert, J. C. Madre, “Towards An Interactive Fault Tree Analyser“, in Proc. of IASTED Conference on Reliability, Quality Control, and Risk Assessment, Washington D.C., USA, Nov. 1992.
  41. O. Coudert, J. C. Madre, “A New Graph Based Prime Computation Technique“, in Logic Synthesis and Optimization, T. Sasao Editor, Kluwer Academic Publishers, pp. 33-57, 1993.
  42. O. Coudert, J. C. Madre, “A New Implicit DAG Based Prime and Essential Prime Computation Technique“, in Proc. of International Symposium on Information Sciences, Fukuoka, Japan, July 1992.
  43. O. Coudert, J. C. Madre, “Implicit and Incremental Computation of Primes and Essential Primes of Boolean Functions“, in Proc. of 29th DAC, Anaheim CA, USA, June 1992. Best paper award
  44. B. Lin, O. Coudert, J. C. Madre, “Symbolic Prime Generation for Multiple-Valued Functions”, in Proc. of 29th DAC, Anaheim CA, USA, June 1992.
  45. O. Coudert, J. C. Madre, “A New Method to Compute Prime and Essential Prime Implicants of Boolean Functions“, in Advanced research in VLSI and Parallel Systems, T. Knight and J. Savage Editors, The
    MIT Press, pp. 113–128, March 1992.
  46. O. Coudert, “SIAM: Une Boite a Outils Pour la Preuve Formelle de Systemes Sequentiels”, Ph.D. Thesis defended at ENST, Oct. 1991.
  47. J. C. Madre, O. Coudert, “A Logically Complete Reasoning Maintenance System Based on a Logical Constraint Solver“, in Proc. ofIJCAI’91, Sydney, Australia, Aug. 1991.
  48. O. Coudert, J. C. Madre, “Symbolic Computation of the Valid States of a Sequential Machine: Algorithms and Discussion“, in Proc. of Int’l Worshop on Formal Methods in VLSI Design, Miami FL, USA, Jan. 1991.
  49. O. Coudert, J. C. Madre, “A Unified Framework for the Formal Verification of Sequential Circuits“, in Proc. of ICCAD’90, Santa Clara CA, USA, Nov. 1990. Distinguished paper. Selected for inclusion in “The Best of ICCAD – 20 Years of Excellence in Computer Aided Design”
  50. C. Berthet, O. Coudert, J. C. Madre, “New Ideas on Symbolic Manipulations of Finite State Machines”, in Proc. of ICCD’90, Cambridge MA, USA, Sept. 1990. Best paper award
  51. O. Coudert, J. C. Madre, “Verifying Temporal Properties of Sequential Machines Without Building their State Diagrams“, in Proc. of CAV’90, E. M. Clarke and R. P. Kurshan Editors, DIMACS Series, pp. 75-84, June 1990.
  52. J. C. Madre, O. Coudert, M. Currat, A. Debreil, C. Berthet, “The Formal Verification Chain at BULL”, in Proc. of EUROASIC Conference, Paris, France, June 1990.
  53. O. Coudert, C. Berthet, J. C. Madre, “Symbolic Manipulations for the Verification of Sequential Machines”, in Proc. of 1st EDAC, Glasgow, UK, March 1990.
  54. O. Coudert, C. Berthet, J. C. Madre, “Verification of Sequential Machines using Boolean Functional Vectors”, in Formal VLSI Correctness Verification, L. J. M. Claesen Editor, North-Holland, pp. 179-196, Nov. 1989.
  55. J. C. Madre, O. Coudert, “Automating the Diagnosis and the Rectification of Design Errors with PRIAM“, in Proc. of ICCAD’89, Santa Clara CA, USA, Nov. 1989. Selected for inclusion in “The Best of ICCAD – 20 Years
    of Excellence in Computer Aided Design”
  56. O. Coudert, C. Berthet, J. C. Madre, “Verification of Synchronous Sequential Machines Based on Symbolic Execution“, in Lecture Notes in Computer Science: Automatic Verification Methods for Finite State Systems, Volume 407, J. Sifakis Editor, Springer-Verlag, pp. 365-373, June 1989.
  57. J. C. Madre, O. Coudert, “Formal Verification of Digital Circuits Using a Propositional Theorem Prover”, in Proc. of IFIP Working Conference on the CAD Systems Using AI Techniques, Tokyo, June 1989.