Olivier Coudert's Blog

So will Buzz and Facebook finally bury Twitter?

Olivier Coudert — Tue, 23 Feb 2010 17:42:51 +0000

Buzz was introduced by Google with much clamor. Since then, we have seen a lot of debate around it: Google stepping into the social media arena cannot go unnoticed. Many quickly saw Buzz as a Twitter killer [...]

Continue reading So will Buzz and Facebook finally bury Twitter?

Is Twitter Flattening? A Short Answer

What is Twitter’s next step?

Formal verification stalling, take two

Olivier Coudert — Mon, 22 Feb 2010 03:57:24 +0000

My last post must have struck a nerve. In this post I ask whether fundamental innovation stalled in formal verification, and I speculate which area the next technological leap will come from. This post received some quite interesting comments. It also brought a counter point by Brian Bailey, partially motivated by his business partnership with Jasper –Brian sits in Jasper’s Technical Advisory Board. Last Friday I had a lively discussion with Rajeev Ranjan (CTO) and Holly Stump (VP Marketing) of Jasper. I am now taking the time to discuss these feedbacks.

My claim is that formal verification has reached a plateau from both the core technology and business point of view.

Yet that does not mean there is no progress! There is a world between creating a brand new technology and using it for an actual working product. This is what the Jasper, Real Intent, Atrenta, OneSpin, and many others are doing, as they creatively use these core technologies to propose new applications.

From the technological point of view, we have experienced steady improvements in many aspects –equivalence checking (EC), sequential verification, abstraction and refinement, etc. The scope of application of formal verification techniques has dramatically increased for the past few years. It has of course benefited from more powerful hardware –faster CPU, larger memory, multi-threading, distributed systems, FPGA. It also benefited from the skilled engineering of the core technologies, to the credit of the many private companies in the field.

But there is no recent verification tool that has been enabled by any new core technology. Nothing wrong with this, it is partially the consequence of a mature industry, where most of the effort goes into improving the customer experience and helping him integrating verification and design/synthesis flow.

When Randy Bryant published his BDD paper in 1986, he revolutionized the field of formal verification with a technology that could address problems previously out of reach. When EC switched from BDD to SAT solvers nearly 10 years ago, it made possible verifying multi-million gate designs against their RTL description. Bounded model checking became a practical approach to sequential property verification. These were disruptive technologies. Where is the next leap?

From the business point of view, force is to admit that the formal verification market has been pretty stable. Most of the ever-increasing design cost is taken by verification, but that does not translate into a fast growing formal verification market. Instead, the more and more daunting verification task benefits simulators more than formal tools. Yes, customers are slow to move to a different verification flow. Yes, the formal verification industry, as the rest of EDA, struggles to find a business model that would bring back a much needed growth. But which application or technology will bring enough value to make the ratio simulation/formal in favor of the later?

Regarding the simulation vs. formal debate, I would recommend reading Chris Wilson’s comment. He agrees with me that formal verification has had a relatively low return on investment. He then argues that simulators will remain the main verification solution, with formal verification technologies under the hood to speed up simulation, to increase coverage, and to help debugging. He may well have a point here.

One aspect that everybody agrees on is that debugging is still a bottleneck in the verification industry. Why does a design fail its functional requirement? Having a counter example (e.g., a sequence of inputs that disproves a safety property) is often not sufficient: the complexity and length of the counter example can make pinpointing the design error very difficult. A failing liveness property cannot be revealed with a finite sequence of inputs. Similarly, there is no tool that provides consistent debugging information explaining why a statement of a RTL description is unreachable. Formal verification techniques can certainly help here, and there are a few available products aiming at the problem.

In conclusion, formal verification as an industry has matured, but is still looking for the market share it deserves. I think there are a lot of opportunities to grow the market. Success may come as an enabler of a better, faster, high coverage, simulation. I rather believe it will come when formal verification allows software and hardware to be verified and debugged in a common, continuous, design flow. And this requires some major technical innovation.

Has formal verification technology stalled?

Olivier Coudert — Mon, 25 Jan 2010 07:15:45 +0000

We all know that functional verification is the costliest and most time-consuming aspect of ASIC design –about 50% of the total cost, and from 40% to 70% of the total project duration. And we all know that simulation is by far the prevalent verification method, even though it is inherently incomplete due to an input space that is too large to be enumerated. So formal verification, which aims at completeness, should be a thriving field, given the impact it can have on the overall cost and schedule of ASIC designs.

There is certainly no lack of competition in formal verification. The big three EDA public companies, Synopsys, Cadence, and Mentor Graphics, have all their own formal verification offering (Formality, Conformal, 0-in), and there are a number of startups, e.g., Jasper, Atrenta, Real Intent, OneSpin, Blue Pearl Software, to name a few. Formal verification products cover a wide range of applications: System Verilog Assertion (SVA) and property checking; RTL static check; equivalence checking (EC); some limited IP verification; clock-domain crossing (CDC) verification; and timing exception verification (false paths and multi-cycle paths).

Looking at the DAC submissions this year though, I am puzzled by the overwhelming number of papers focused on increasing simulation speed and coverage, as opposed to the handful of papers discussing formal techniques. And this year is not different from last year. And the year before last. Does that mean there is a lack of innovation in formal verification core techniques?

Improving simulation –higher coverage, less patterns, more automation— with formal techniques is a very active field, both in the academic and industrial world. Some inject faults in the RTL to separate the most discriminating patterns (e.g., Certess). Others use SAT and integer constraint solvers to reduce the number of patterns, or to automatically generate patterns for hard-to-cover code branches (e.g., NuSym). But success is all relative. Certess was quickly acquired last year, while NuSym is actively looking for a buyer. There are also semi-formal tools, mixing simulation and state exploration techniques (e.g., Magellan), but they a have limited usage.

What about the more fundamental formal verification technologies? The 80’s were dominated by the development of rigorous semantics models (e.g., multi-valued logic, Verilog and VHDL operational semantics for synthesis and simulation, temporal logics, and synchronous languages like Esterel and Lustre) and the introduction of BDDs. The 90’s saw EC tools spreading in the industry and the rise of model checking. The 00’s were all about SAT and model abstraction to push the capacity of EC and bring property checking to the end-user, as well as static code analysis, CDC, and timing verification. What are we going to see in this decade?

Verification has a lot of challenging problems, with incomplete or no solution at all. Here is my list:

Merged arithmetic. There are robust methods to verify adders and multipliers of practically any size, but no one can verify merged arithmetics as small as 32-bits.
Low power. This leads to complex properties capturing the correctness of sequential clock gating and power gating. The former is becoming more common, and there are techniques to address most of it (e.g., Calypto and Conformal). But the later is still waiting for a comprehensive and automated solution.
RTL debugging. There are a number of static code checkers, but debugging is still very poor.
HW/SW verification. Can we leverage deductive methods (predicate logic, HOL, rewriting system) to close the gap between software and RTL?
Mixed signal (analog/digital) devices: this is a very young area of research, but it should see a lot of focus given the increasing ubiquity of mixed signal designs.

If formal verification core technology is to evolve, we will see some original solutions to the problems listed above. What do you think should be added to this list? And which techniques will evolve as the most promising?

UPDATE: I had enough interesting comments and feedback about this post to motivate a follow-up post.

Twitter and snowflakes

Olivier Coudert — Wed, 20 Jan 2010 03:50:48 +0000

5NX9DCF979QD According to the official weather service, the UK has just suffered through its longest spell of freezing conditions since December 1981.

The recent winter storms across the whole of the UK wreaked havoc with public transport and generally disrupted the lives of millions of UK residents. Soon hundreds of thousands of UK residents turned to a Twitter-based application, the UK Snow Map. Created by freelance web developer Ben Marsh and powered by 34SP.com, the application lets Twitter users report where snow is falling and by which amount. It displays the reports in real-time on a map of the UK. It works regardless of the cloud cover, unlike weather satellites.

The system is deceptively simple: anyone with a Twitter account can report on her local snow conditions with the hashtag #uksnow. She rates the snowfall from 0 (no snow) to 10 (blizzard), and specifies her location using the name of the town or the ZIP code –no geo-tag support yet. Those tweets are then analyzed and placed on a map of the UK, giving a real-time visual picture of the local snow conditions as reported by actual residents on the ground.

The UK Snow Map has been active since February 2009, and has seen a huge increased in use, mirroring the Twitter popularity in the UK, as well as this year’s harsh winter. At the height of the snowfall last week, the map received 50,000 visits in one day –as many as the total number of visits it received last year. During the recent wintry weather, the application processed over 100,000 unique snow reports from all over the UK, with rates of over 100 tweets per minute at peak times.

Next step, using geo-location and more hashtags for real-time maps of fog and rain? Or to-the-minute traffic info? What kind of application would you build on top of it?

Did you feel the tremor? The 2010 challenges for EDA

Olivier Coudert — Fri, 15 Jan 2010 07:39:14 +0000

Yes, did you feel it? No, I am not talking about the two earthquakes that I felt last week in San Jose, shaking the buildings, and leaving people with that weird feeling that they just experienced a whisper of the Big One to come. No, I am talking about the tremor in the US economy. And, closer to me, in the EDA ecosystem.

After about a year of seeing a desolated EDA landscape, littered with startups that could not find the money to survive to the next decade, or with promises that faltered as the semiconductor industry was hit hard with inventories it could not clear, the beginning of 2010 is suddenly looking brighter. Well, not as bright as I would like it to be, but there is definitely a sense of revival.

The semiconductor industry is announcing better-than-expected numbers for CY09Q4, and the recent Consumer Electronic Show (CES) led new expectations for exciting products that should be available within the year. How will this impact EDA? If impact there is, it will not be immediate, as many of its customers are still holding on their investments for the rest of the year, since most of their designs can be done with their current flows and tools. But, as pointed out by Richard Goering, CES showcased the hot products to come, and some will definitely require EDA tools to step up. Whether it is tablet PCs, ever more powerful mobile phones, 3D-TVs (over-hyped, if I may say so), USB 3.0, or wifi-enabled cars, there are plenty of avenues where mixed signals, low power, packaging, and high-capacity SoC design and verification tools can shine.

These are all familiar topics, but CES stressed the need for better, automated, and scalable solutions.

Mixed signals will help Cadence –Synopsys does not have a credible solution there, and Magma is still too young in this market to push its Titan offering, regardless of its technical merits.
Low power will be a leveled field, because there is no one-vendor comprehensive solution covering all its many facets; e.g., CPF/UPF support (Cadence and Synospys-Mentor-Magma respectively); RTL-level low power synthesis, which requires complex IP or/and manual architecturing; power-efficient clock tree synthesis, best done by Azuro and Mentor’s Olympus; and last but not least, low power verification, still led by Cadence’s Conformal.
Early packaging estimation will be an interesting challenge –table PC and mobile phones require very thin, heat-dissipating, robust devices. Mentor and Cadence should capitalize on some of their technology and experience there.
Large SoC design and verification is becoming more acute. Synospys and Mentor look positioned to make a move against an aging First Encounter-based Cadence solution.

It is still difficult to find money to finance new ventures or keep existing startups alive, so predicting what will come from startups is quite difficult for 2010. We will surely see whether Oasys, with its promise of 10-50x larger and faster synthesis, are for real. We will see whether ATopTech can separate itself from the increasingly commodity-like backend offering. We may see whether ESL or some flavor of C/C++-based hardware design environment can help addressing SoC challenges –for designing and verifying both the silicon and the software.

There is a window of opportunities driven by a recovering consumer electronic market, where EDA can demonstrate that innovation and responsiveness to the next technological challenge does pay off. Let the game begin.

Is Twitter Flattening? A Short Answer

Olivier Coudert — Tue, 12 Jan 2010 22:19:31 +0000

Compete and Quantcast have now released their latest data about the traffic on Facebook, MySpace, and Twitter for December. According to Compete’s report, twitter.com’s US traffic reached 22.81 million unique visitors [...]

Continue reading Is Twitter flattening? A short answer

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End-of-the-year reflection: what is it to blog in EDA?

Olivier Coudert — Wed, 30 Dec 2009 01:27:28 +0000

It is not quite yet the last day of the year, but two days to go is good enough to reflect on my recent blogging experience. I published my first post on September 14 of this year. Starting from scratch is always difficult, and starting a blog nowadays means you have to compete with millions of already established writers out there.

Well, not millions after all. I have been writing mostly on EDA and related subjects, like outsourcing, software quality, and FPGA, covering both technical and business aspects; this is of interest to only a few tens of thousands of people. Most of these posts were featured in Design & Reuse, EDACafé, and CodeProject. Simply put, Design & Reuse has been for me the greatest portal to get an EDA audience to read my blog, right next to LinkedIn. Interestingly enough, quite a lot of traffic came from Yahoo finance because of two posts I had on Xilinx’ and Altera’s financial results. The fastest growing audience vector has been Twitter. I really started to use Twitter in September, and only now I can see Twitter to carry some significant interest from followers and retweets to my blog. It has been great to see comments and discussions unfolding around topics I discussed on this site.

One of my early blog, about why FPGA startups keep failing, captured a lot of interest. I had many comments on the blog, messages via LinkedIn, or direct feedback by email. But that post had an early start, so somehow I do not consider it as the most successful. The one that clearly hit a nerve is the post where I discussed EDA versus VLSI service companies. Two days after being published it racked up the number two spot of the most popular posts, and it triggered very interesting exchanges with a number of people in the industry.

After its inspection three months on a half ago, the twenty posts of my blog received just short of 10,000 views. I was glad to see one of my posts in the notable EDA blog postings for 2009 list of Richard Goering. EDA has been my passion for 20 years, still is, and it is exciting to establish new connections and opportunities via this blog.

But I have to admit that the traffic I draw to this blog is nothing compared to a handful of posts I wrote for TheNextWeb and Neowin. It was a great experience to write as a freelance and guest blogger, and I intend to pursue writing editorial, analysis, or opinion pieces for these high quality tech news sites.

I enjoy the interaction resulting from my writing about topics I care about. I hope that you, reader, enjoy it too. Let us meet again in 2010 on this site for more discussions.

I wish you a happy new year!

Why starting a blog in the first place?

Why service companies will eat up EDA

Olivier Coudert — Fri, 11 Dec 2009 23:27:07 +0000

Over the past week we heard good news from Xilinx and Altera, both raising their revenue targets for Q4CY09 (Q3FY10 and Q4FY09 respectively). Both of the FPGA giants are doing fine, and are poised to grow twice as fast as the semiconductor industry. The semiconductors companies are doing well too, with TI upping its Q4CY09 guidance, National leading the forecast in industrial demand, UMC and TSMC reporting a year-to-year sales increase of 52% in November, and the overall chip sales growing 14% year-to-year in October.

It is good to learn that the customers of the EDA industry are doing better –if they do badly, EDA will do too. But will that seemingly economic improvement of the semiconductor industry translate into better days for EDA? Nothing is less certain. The recent quarterly reports of Synopsys, Mentor, Cadence, and Magma, although slightly above guidance, show a bleak outlook. Most of the book-to-bill ratios decreased, and they all carefully announcing a lean year ahead.

I recently ran into some acquaintance working for a leading semiconductor company (in the top 15), who told me that they are reaching out to services companies to get more values out of them. The numbers speak for themselves: they will put $12 millions down for an evaluation project that will encompass the full backend part of the design cycle –about 8 months project. That is only for an evaluation! When was the last time any EDA company was given that amount of cash for a real-life trial?

More numbers? Let us only look at the VLSI service companies in India, i.e., in no specific order: HCL Technologies, KPIT Cummins Infosystems Ltd, MindTree Ltd, Sasken Communication Technologies, Tata Consultancy Services, Wipro Technologies. According to the India Semiconductor Association, VLSI design service revenues in India could hit $1.13 billion in 2009, while hardware and board design could reach $560 million and embedded design and services about $7.29 billion. Yes, that’s nearly $9 billion overall, nearly twice the EDA market, and China is not even in the picture yet. Despite the dramatic downturn in 2009, some of these services companies did quite well, and most expect an uptick with a recovery in the semi industry next year.

The truth is that EDA companies have been providing software solutions that are more and more seen as commodities. The license renewal rate is dropping and its volume is decreasing. In a flat, if not slowly shrinking market, the EDA firms have to eat their competitors’ share if they want to grow or just survive. They drop their prices and fork free AE support to sweet the deal for the customer. The vast majority of the designs can be done with last year’s generation suite, thus there is no urgency to buy new design tools. Then semiconductor companies might indeed be better off with a dedicated service company, which provides hands-on design expertise, and will be judged on results, i.e., the final tapeout. This is a win-win situation: the customer can fully rely on the service company, and since this business model commands a much higher fee than for a software license, the service company can expand and further invest to be an intimate part of their customers’ flows.

EDA has better look around and see what is happening. Semiconductors companies will more and more rely on service companies, tailored to their needs. Chip design and verification looks more and more like an IP assembly that requires an expertise that EDA tools do no longer deliver. The value-added is in that expertise, not in the tools that are becoming more and more push-process.

It is true that VLSI service companies buy tools to EDA companies, but the service companies factorize the license usage between several customers, which means that overall, less licenses are needed. Today, TCS can easily rent any EDA tool from the big 3 by the week or by the month. Imagine tomorrow Synopsys, Cadence, and Mentor dealing only with the top 6 hardware design service companies, themselves servicing the top 20-30 in the semi industry: EDA will loose a lot of leverage in the sale negotiation process. If Magma ends up as a cheap provider of IC implementation solutions, all developed in India, it will lower the bar even more.

EDA has to evolve quickly if it does not want to be sidelined as just an enabler. The EDA industry must be part of the design expertise, and work closely with its customers, even if it means its solution is no longer generic. And yes, as I said in the past, the value-added is in the system-level software, and this is where resides the growth of hardware designs. So the EDA industry must go into chip software design and verification if it wants to be relevant in five years from now.

The truth about Twitter usage

Olivier Coudert — Wed, 02 Dec 2009 23:46:11 +0000

Three research firms reported traffic to Twitter.com dropping between the month of September and October. According to these firms, the number of unique US visitors to the Twitter website went down [...]

Continue reading The truth about Twitter usage

Related posts:Is Twitter Flattening? [...]

Continue reading The truth about Twitter usage

Twitter sure is a rollercoaster, but going up or down?

Olivier Coudert — Tue, 24 Nov 2009 15:53:22 +0000

The last 10 days have been pretty interesting to follow in the fast moving world of Twitter. They showed a contrasting (or seemingly so) picture of where the super-hyped company is heading. Let us rewind the last few events [...]

Continue reading Twitter sure is a rollercoaster, but going up or down?