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No doubt that for the next two weeks you will find many DAC reports in blogs and corporate marketing websites. So I tried not to write yet another DAC report, with a long list of companies and products. Instead, I have chosen to share my absolutely non-exhaustive, completely biased view of DAC. I will [...] Continue reading DAC 47th digest: what you missed (even if you were there) Xilinx announced that it signed a multi-year strategic licensing agreement to use Oasys’ synthesis. What does that mean for the FPGA and EDA community? Oasys’ product, RealTime Designer, is claimed to be 10x-60x faster than the competition. Among other things, it uses AIG-based optimization. This technology is best illustrated by UC Berkeley’s ABC synthesis: [...] Continue reading Who should worry about Xilinx and Oasys partnership? Cadence unveiled EDA360 in April. Now that I found the time to read its 28-pages white paper, I can finally comment on it. EDA360, John Bruggeman’s brainchild, is a manifesto that promotes a vision for the future of EDA. In a nutshell, it states the following: So far EDA has been providing the tools [...] Continue reading What you need to know about EDA360 A FPGA company makes revenue with the hardware: it sells its device, and gives away its design tools –synthesis, place-and-route. Yet the EDA industry has had success with its own (non-free) FPGA synthesis solutions. For good reasons: in its days, Synplicity’s Synplify was the best FPGA synthesis out there. Synopsys acquired Synplicity two years [...] Continue reading Is FPGA a sustainable market for EDA? The past two weeks were pretty interesting if you follow FPGAs. Yes, Xilinx and Altera kept upping their target to Wall St., but that is not where the excitement came from. It came from the recent announcements of two startups, both created in 2003 and heavily funded. Tabula released its long-awaited device, which goes [...] Continue reading Can Tabula and Tier Logic be successful? My last post must have struck a nerve. In this post I ask whether fundamental innovation stalled in formal verification, and I speculate which area the next technological leap will come from. This post received some quite interesting comments. It also brought a counter point by Brian Bailey, partially motivated by his business partnership [...] Continue reading Formal verification stalling, take two We all know that functional verification is the costliest and most time-consuming aspect of ASIC design –about 50% of the total cost, and from 40% to 70% of the total project duration. And we all know that simulation is by far the prevalent verification method, even though it is inherently incomplete due to an [...] Continue reading Has formal verification technology stalled? Yes, did you feel it? No, I am not talking about the two earthquakes that I felt last week in San Jose, shaking the buildings, and leaving people with that weird feeling that they just experienced a whisper of the Big One to come. No, I am talking about the tremor in the US [...] Continue reading Did you feel the tremor? The 2010 challenges for EDA It is not quite yet the last day of the year, but two days to go is good enough to reflect on my recent blogging experience. I published my first post on September 14 of this year. Starting from scratch is always difficult, and starting a blog nowadays means you have to compete with [...] Continue reading End-of-the-year reflection: what is it to blog in EDA? Over the past week we heard good news from Xilinx and Altera, both raising their revenue targets for Q4CY09 (Q3FY10 and Q4FY09 respectively). Both of the FPGA giants are doing fine, and are poised to grow twice as fast as the semiconductor industry. The semiconductors companies are doing well too, with TI upping its [...] Continue reading Why service companies will eat up EDA |
 
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