|
||||||
|
My last post must have struck a nerve. In this post I ask whether fundamental innovation stalled in formal verification, and I speculate which area the next technological leap will come from. This post received some quite interesting comments. It also brought a counter point by Brian Bailey, partially [...] Continue reading Formal verification stalling, take two We all know that functional verification is the costliest and most time-consuming aspect of ASIC design –about 50% of the total cost, and from 40% to 70% of the total project duration. And we all know that simulation is by far the prevalent verification method, even though it is inherently incomplete due [...] Continue reading Has formal verification technology stalled? Yes, did you feel it? No, I am not talking about the two earthquakes that I felt last week in San Jose, shaking the buildings, and leaving people with that weird feeling that they just experienced a whisper of the Big One to come. No, I am talking about the tremor [...] Continue reading Did you feel the tremor? The 2010 challenges for EDA Over the past week we heard good news from Xilinx and Altera, both raising their revenue targets for Q4CY09 (Q3FY10 and Q4FY09 respectively). Both of the FPGA giants are doing fine, and are poised to grow twice as fast as the semiconductor industry. The semiconductors companies [...] Continue reading Why service companies will eat up EDA ICCAD’09 was a fairly good vintage. It started Monday morning with an excellent keynote from Hamid Pirahesh about cloud computing. The same day in the afternoon, a more EDA-focused discussion was initiated by Jim Hogan and Paul McLellan (slides can be found here), asking the [...] Continue reading What EDA needs to change for 2020 success? Functional verification is a major bottleneck in the chip design cycle. Any misstep in closing the functional correctness of a digital system costs millions of dollars in redesign, additional testing, and silicon respins. One can argue at length about its actual cost, but people in the industry usually agree that functional [...] Continue reading The formal verification market is still untapped
Continue reading Test-driven design, a methodology for low-defect software I built up products from scratch several time in my professional life. Usually it starts with a very small engineering team –sometimes I was the very first member of the team. This is a great opportunity to lay strong foundations for the subsequent software development, because one is in [...] Continue reading API design 101 A previous post showed a very-high level view of low power design with UPF/CPF. Power gating, a must-do for mobile products, is still a very manual process, and verifying the correctness of its implementation is a very challenging task. In this follow-up post, I single out some aspects of the power-gating flow, [...] Continue reading Automated low-power design flow is up for grabs (Part II) Low power is becoming more and more critical as the number of mobile and wireless applications is increasing. Battery life is a feature that can make the difference between a success and a flop. Remember the first version of the iPhone? All praised the touch screen interface, but so many criticized its [...] Continue reading Automated low-power design flow is up for grabs (Part I) |
 |
|||||
|
Copyright © 2010 Olivier Coudert's Blog - All Rights Reserved |
||||||
