Tier Logic had a unique value proposition: you could turn its FPGA into an ASIC in a predictable time and cost. It had a working silicon and a proven production tool, and achieved to do so with spending only $20M.

It is a pity to see that a company with such a good technology and such an attracting business proposition must shut down because of lack of interest from VCs. You have to wonder which strings you have to pull in the investment community to get the attention you deserve.

Although Tier Logic will likely attempt to sell its technology to a Xilinx or an Altera, it is also quite likely that whoever the buyer is will simply buy Tier Logic’s patents to bury them. Too bad.

After Abound Logic‘s shut down 6 weeks ago, another startup showing how hard it is to be successful in FPGA.

Related posts:

1. Can Tabula and Tier Logic be successful?
2. RIP Abound Logic
3. Why FPGA startups keep failing

Instead, I have chosen to share my absolutely non-exhaustive, completely biased view of DAC. I will then publish a couple of posts focused on specific themes in the next few days.

Attendance

The 47^th DAC was held June 13-18 at the Anaheim Convention Center in California. The preliminary attendance numbers are reported as follow:

• Total full conference: 1554
• Total exhibit attendees: 3444 (24% international)
• Exhibitors, visitors, and guests: 2557
• Total attendees: 6001

The final attendance numbers are usually a few percent higher.

For a fair comparison, I pulled out the preliminary attendance numbers of the past conferences. I was first fooled by the way the numbers were labeled this year –see the comments below, and a big thanks to Sean to bring me the correct interpretation. The table below shows the correct data, excluding booth staff. It shows a sharp decline (33%) of the total attendance compared to last year in San Francisco. Not having DAC in San Francisco means higher cost for most of the attendees –many of them are from the Silicon Valley–, which is clearly reflected in the attendance numbers.  But if we compare this year’s numbers with the 2008 DAC venue held at the same location, we see the same sharp decline (28%). Note the drop in exhibits-only attendees (-41% w.r.t. 2009, -21% w.r.t. 2008), not a good sign as this number captures most of the customer audience.

DAC preliminary attendance numbers (not including booth staff)

This year’s DAC comes after one of the worst recession, but looking forward to a very strong semiconductor growth in 2010 and 2011, which should eventually translate into a mildly better business for EDA. The exhibition was well attended on Monday, with a sharp decline on Wednesday –lots of people left by that time.

The buzz

With Cadence’s EDA360 campaign in the background, and the fresh acquisitions of Denali by Cadence and Virage Logic by Synopsys, it felt that IP was the buzzword of the day. IP design here, IP verification there, verification IP everywhere, the overall SoC design looked like an IP integration problem that EDA was gearing up to take on. Embedded software and ESL were also showcased by Cadence and Mentor Graphics as part of their SoC focus.

Verification

There was a booth dedicated to UVM/OVM (Universal Verification Methodology/Open Verification Methodology). These methodologies offer open and interoperable verification solutions. They both support multiple languages and simulators, and enable verification IP, so critical to SoC design. The message was well received and had a strong attendance.

Still on the verification side, new products and startups are trying to repeat the success of Certess (acquired by SpringSoft last year). Advanced formal verification tools (e.g., property checkers) are slow to find acceptance by the design community. Instead these new products and startups leverage the existing test bench and simulation methodology in place to produce better coverage or faster simulation. Notably missing in this space was NuSym, a no-show at this year’s DAC, confirming the rumors that the startup that demonstrated “intelligent” simulation two years ago is actively looking for a buyer.

The whole simulation and emulation space was strong. Mentor’s Veloce is showing impressive numbers, and is ready to take on Cadence’s Palladium. Eve will likely take notice, and this may bring it closer to Synopsys.

Magma’s Tekton offers sign-off quality multi-mode/multi-corner static timing analysis for multi-million gate circuits. The tool has been designed from the ground up, and tailored for multi-threading and distributed systems. It is a clear competitor to Synopsys’ PrimeTime, even though running PrimeTime *is* the signoff for most customers.

Design and implementation

On the P&R and backend side, nothing really stood out. Synopsys clearly gained in QoR, Mentor’s momentum with Sierra’s Olympus is still strong, and Magma keeps lagging behind, especially in runtime. Atoptech and Azuro, although showing pretty good numbers (verified at customers’), are still considered more like add-ons that comprehensive solutions. This segment looks more and more commoditized, and only the high-end (20nm and below) and 3D seem to offer new growth opportunities in that space.

Oasys, the darling of last year’s DAC, did not make as much as a splash this time, despite its recent announcement with Juniper Networks and Xilinx. Nobody question the speed and capacity of their tool, as well as the clock cycle it can achieve. But some raised concerns regarding the area of their netlists for ASIC.

On the fringe

This is the “stuff I liked that may be too small to be noticed”, even more so since two of these three companies didn’t have a booth at DAC…

Low power is still under-represented, even though power gets worse with smaller geometries, and power management remains mostly a very manual process. In that space I liked Docea Power, which can simulate system-level models to analyze power consumptions and thermal behaviors. System-level analysis can bring the biggest power savings. It also has a significant impact on the packaging, which is still a domain where conservative approaches are preferred to more cost-efficient, but riskier, choices.

A comprehensive system-level design framework is really an IDE (Integrated Development Environment) for SoC, where hardware and software can be designed together, written and simulated together, and where the HW/SW tradeoffs can easily be explored. IDEs have been used in software for a long time, but are a novelty to hardware designers. Sigasi proposes an IDE for VHDL –what Microsoft’s Visual Studio is to C++. Although this is still light-years away from a SoC IDE, this is a hint into the future of writing RTL.

We heard several claims that cloud computing is coming to EDA (or the converse?). Xuropa best illustrates that (slow) move. They provide turn-key online community solutions for the electronic design industry. Their main customers, Cadence and Synopsys, are using the services for CRM and virtual demo only. But Xuropa could become a platform that enables collaborative design in the cloud, providing secured access to a multi-vendor flows. More on this in a future post.

Last words

I felt that there was a lot of system-centric messages (best captured by EDA360), and attempts at rising the abstraction level for higher productivity. EDA vendors are forced to see the big picture –full system design, software and hardware together. But as pointed out by Steve Jones (TI) at Cadence’s Silicon Realization Luncheon, EDA is still missing out on two important parts of the SoC design. One is that customers want a first-silicon that is functionally operational, and Steve singled out the need for useable verification IP –UVM/OVM is a step in the right direction. The other is analog –mixed-signal design is the rule, and there is no good integration there.

Related posts:

1. Did you feel the tremor? The 2010 challenges for EDA
2. The formal verification market is still untapped
3. Has formal verification technology stalled?

Abound logic, previously known as M2000, was founded by three EDA veterans who had previously started Meta Systems. Meta Systems developed the industry’s first emulation system based on custom FPGAs, which was to become the basis for the Abound Logic device after Meta Systems was acquired by Mentor Graphics in May 1996.

Abound logic’s device, the Raptor FPGA, offered in 65nm technology the capacity of 774k CLBs, each containing a 4-input LUT. This made the Raptor the largest FPGA on the market at a time.

Abound logic was in discussions to close another financing round, estimated around $20M, but one of the main tentatively new investor pulled out, which put to rest the last investment opportunities.

Related posts:

1. RIP Tier Logic
2. Can Tabula and Tier Logic be successful?
3. Why FPGA startups keep failing

The dominant factor in classical FPGA architecture is the interconnect: most of the die area is taken by the wires and the interconnect switches and muxes. If you can somehow reduce the area dedicated to interconnect, you can augment the logic density and lessen the cost of the device. Tabula and Tier Logic pitch a 3D architecture to address the interconnect bottleneck, albeit in very different flavors.

Tabula innovative design is based on its ability to reconfigure itself, up to 8 times with a clock running at 1.6GHz. At each cycle a cell can change its functionality, its latch configuration, and its interconnect. The time-multiplexing increases the amount of logic that can be fit on the same area. It is like having 8 layers (or “folds”) of cells stacked on top of each other along a time axis, with very short connection between cells at the same (x,y) coordinate but in two adjacent folds. At each cycle one jumps to the next fold and feeds the new configured logic with the results of the previous fold. Tabula claims they increase the logic density by 2.5x compared to classical FPGA architectures.

Tier Logic’s design idea is to place the SRAM cells that configure the interconnect muxes on top of the routing layers, instead of having them distributed throughout the logic die area. Doing so leaves more room for logic cells, increasing the cell density by about 50% according to the company. The design flow will not throw anybody off: it uses Mentor’s Precision for synthesis, and is followed by Tier Logic’s mapping and P&R.

A big plus touted by Tier Logic is the ability of moving painlessly from their device to an ASIC. Simply replace the interconnect configuration SRAM cells at the top with metal, and voila, you obtain an ASIC with no change in timing. This is a simple, predictable process: it takes about 4 weeks to go from the SRAM configuration to a top-layer mask, and you do not need to go through a timing closure flow again, which means a non-recurring engineering cost of about $50k. This is a real bargain when you consider that moving from FPGA to ASIC usually requires a redesign that can take as long as 9 months.

So who of Tabula and Tier Logic is best positioned to challenge the duopoly Xilinx/Altera?

Tabula made it clear that they are aiming at the high-end of the FPGA market. There are a number of FPGA startups that targeted the same niche, and none survived. One reason is that it is easy for Xilinx and Altera to increase the size of their device, by simply moving to the next technology node. Tabula’s design is innovative and pushes the limits, but how far is too far? It is unclear whether the company can deliver the design tools to match their device’s challenges –they went through a complete reset a few years ago, replacing the whole software team. Verifying a device that can reconfigure itself 8 times in a loop may be another challenging problem. Increased density is obtained by continuous reconfiguration, which means extra power consumption: is it still an acceptable tradeoff? Last but not least, with 100+ people in the US, it is a well-known fact in the Silicon Valley that Tabula burns cash fast, and their funding of $106 millions so far is about to come short.

Tier Logic’s FPGA can reduce the cost of the device for the same density. But their compelling value proposition is really their FPGA to ASIC translation. This is what Altera’s HardCopy was supposed to be, a seamless and risk-free migration from FPGA to ASIC. For anybody that wants to design an application and then migrate to a low/medium volume ASIC production, this could be the most cost efficient solution. I do not know the inside story regarding the financial aspect, but their business proposal looks more solid.

So who do you think has a chance here? Let’s meet again in 3-4 quarters and see how the two companies are doing.

Related posts:

1. RIP Tier Logic
2. Why FPGA startups keep failing
3. RIP Abound Logic

It is good to learn that the customers of the EDA industry are doing better –if they do badly, EDA will do too. But will that seemingly economic improvement of the semiconductor industry translate into better days for EDA? Nothing is less certain. The recent quarterly reports of Synopsys, Mentor, Cadence, and Magma, although slightly above guidance, show a bleak outlook. Most of the book-to-bill ratios decreased, and they all carefully announcing a lean year ahead.

I recently ran into some acquaintance working for a leading semiconductor company (in the top 15), who told me that they are reaching out to services companies to get more values out of them. The numbers speak for themselves: they will put $12 millions down for an evaluation project that will encompass the full backend part of the design cycle –about 8 months project. That is only for an evaluation! When was the last time any EDA company was given that amount of cash for a real-life trial?

More numbers? Let us only look at the VLSI service companies in India, i.e., in no specific order: HCL Technologies, KPIT Cummins Infosystems Ltd, MindTree Ltd, Sasken Communication Technologies, Tata Consultancy Services, Wipro Technologies. According to the India Semiconductor Association, VLSI design service revenues in India could hit $1.13 billion in 2009, while hardware and board design could reach $560 million and embedded design and services about $7.29 billion. Yes, that’s nearly $9 billion overall, nearly twice the EDA market, and China is not even in the picture yet. Despite the dramatic downturn in 2009, some of these services companies did quite well, and most expect an uptick with a recovery in the semi industry next year.

The truth is that EDA companies have been providing software solutions that are more and more seen as commodities. The license renewal rate is dropping and its volume is decreasing.  In a flat, if not slowly shrinking market, the EDA firms have to eat their competitors’ share if they want to grow or just survive. They drop their prices and fork free AE support to sweet the deal for the customer. The vast majority of the designs can be done with last year’s generation suite, thus there is no urgency to buy new design tools. Then semiconductor companies might indeed be better off with a dedicated service company, which provides hands-on design expertise, and will be judged on results, i.e., the final tapeout. This is a win-win situation: the customer can fully rely on the service company, and since this business model commands a much higher fee than for a software license, the service company can expand and further invest to be an intimate part of their customers’ flows.

EDA has better look around and see what is happening. Semiconductors companies will more and more rely on service companies, tailored to their needs. Chip design and verification looks more and more like an IP assembly that requires an expertise that EDA tools do no longer deliver. The value-added is in that expertise, not in the tools that are becoming more and more push-process.

It is true that VLSI service companies buy tools to EDA companies, but the service companies factorize the license usage between several customers, which means that overall, less licenses are needed. Today, TCS can easily rent any EDA tool from the big 3 by the week or by the month. Imagine tomorrow Synopsys, Cadence, and Mentor dealing only with the top 6 hardware design service companies, themselves servicing the top 20-30 in the semi industry: EDA will loose a lot of leverage in the sale negotiation process. If Magma ends up as a cheap provider of IC implementation solutions, all developed in India, it will lower the bar even more.

EDA has to evolve quickly if it does not want to be sidelined as just an enabler. The EDA industry must be part of the design expertise, and work closely with its customers, even if it means its solution is no longer generic. And yes, as I said in the past, the value-added is in the system-level software, and this is where resides the growth of hardware designs. So the EDA industry must go into chip software design and verification if it wants to be relevant in five years from now.

Related posts:

1. What EDA needs to change for 2020 success?
2. Software outsourcing, a necessary evil
3. How can Xilinx improve its bottom line

Continue reading Twitter sure is a rollercoaster, but going up or down?

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Paul rightly emphasized three trends. The first one is well know: the continuously rising cost of IC designs, about $50M for today’s 45nm node. The second trend is that the fastest growing part of the design cost is software –more than half of the overall cost, Paul even claiming close to 2/3 of the overall cost. The third trend is an increasingly fragmented consumer market: the number of end products goes into the 10’s of billions, but these products are declined in many more different kinds, which means that most of them are shipping in smaller individual volumes.

Source: Morgan Stanley, Economy + Internet Trends, Web 2.0 Summit, San Francisco, Oct 2009.

This is bad news for EDA as we know it: the rising cost of design can no longer be justified if the number of units does not grow fast enough (a $50M chip starts to make sense only if it is produced for 250M units and more). Also EDA has been slow to climb up the food chain and proposes solutions for software design, which dominates the overall chip design cost.

Rising IC design cost and smaller number of units is the call for FPGA to growth even faster. Mobile applications require FPGA to do much better in terms of power consumption, but this is a hot topic (no pun intended) drawing a lot of attention and investment, and some competitive solution will emerge in the next few years. So EDA, which makes its bread and butter on IC design, should better re-align its growth strategy on software, embedded systems, HW/SW co-design, and verification. Else EDA will continue to shrink to only service the few that can still afford chip design.

The end product, as a SoC, is a puzzle where the designer mostly assembles existing cores and IPs, and decides of the tradeoff between the software and hardware parts, based on flexibility and cost factors.

I see two strong needs that EDA could build its growth on. One is functional validation of the whole system –software plus hardware. EDA has started to address the issue, even though it is still short of proposing a scalable and automated environment. To functional validation, I would also add functional flexibility: how much of the behavior can be upgraded thanks to the software part? The other need is a design navigator that would estimate the speed, area, power consumption, and cost of a SoC by exploring alternatives between cores (ARM, MIPS, etc), IPs, FPGA, and software.

Last but not least, the eternal question of an EDA serving a $250B semiconductor industry, but making less than $5B. The time-based license model has only served the interests of the semiconductor companies, to the expenses of R&D investment in EDA. Claiming a lack of innovation in the EDA industry is sometimes fair, but EDA should also innovate in business solutions instead of cannibalizing itself by cutting costs to only survive another quarter. The semiconductor industry needs a healthy EDA if it wants to address the system-level design challenges of the next 10 years. Unless, of course, a new player coming from the software world with the experience of scalable systems signs the death of the EDA industry as we know it.

Related posts:

1. The formal verification market is still untapped
2. Why service companies will eat up EDA
3. Is FPGA a sustainable market for EDA?

Continue reading What is Twitter’s next step?

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Comparing the yearly fiscal exercises directly would be biased (Xilinx’ fiscal year end on March 31^st, and Altera’s fiscal year on Dec 31^st). Instead we can look at a quarter by quarter comparison, even though that can be too low a level. Better is to look for ttm (trailing twelve months) comparison to smooth out the local variations.

Source: Yahoo! Finance. All figures in thousands.

One can see that Altera’s operating margin is overall better. Also in their respective Q3’09 revenue reports, Xilinx expects its Q4’09 gross margin to improve to 62-63%, and Altera sees his to be 67-68%.  So a 3-4% operating margin gap will remain, which is significant.

On the other hand, Xilinx quotes 3145 full time employees, and Altera 2760. This means that a Xilinx employee brings back revenue about 26% higher than an Altera employee! So it all boils down to the question: how can Xilinx be more cost efficient?

One of the differences is the way software is developed. Altera’s software is mostly done in their technology center of Penang, Malaysia, with a very small core technology group in Toronto, Canada. Xilinx’s software team is mostly in the US, and only 5% of the team is in their R&D facilities in Hyderabad, India. A back-of-the-envelop calculation shows that if Xilinx had the same software team but with a US/India ratio 1/3-2/3, which is a healthy ratio for a company that can leverage its India facility, Xilinx would improve its operating margin by one point.

If you extend the same reasoning to whole R&D –not only software–, then it is clear that Xilinx can get the upper hand. Looking at the R&D job listings, it is also clear that Xilinx is moving into that direction. The question then is whether Xilinx has the structure and the drive to achieve such a transformation successfully.

Related posts:

1. What to read in Xilinx’ and Altera’s third quarter results
2. Who should worry about Xilinx and Oasys partnership?
3. Software outsourcing, a necessary evil

The breakroom had a tweeter wall with live reaction of the attendance –hashtag #tcm09, check it out.

The first to present was Mathias Roth from iOpus.com. His message was quite simple: if you are a startup that wants to get attention, be the first to develop for a new platform, any new platform. The rational: if you are among the first, chance is that you will stick. Look at the top 50 add-ons to Firefox today: half of them have been introduced within the year Firefox made its add-ons development platform available. Mathias’ recommendation: get on Chrome’s bandwagon and develop your add-on now –there are only about 25 Chrome add-ons today. Even though Chrome’s add-ons website will not come before the end of the year, it will pay to be among the first.

Next speaker was Rainer Maerkle from Holtzbrinck Ventures. He gave a great talk about what it takes to launch a startup. I will not do justice by trying to reduce his talk to a few words, but it would come as something like: do your homework, focus, take risks, focus, execute, focus. Oh, and don’t wait for VC money, or don’t over-specify your product: just do it and get it out, then release often.

Then come the exciting part: 12 startups pitching for 3mn each + 1mn for question. Some did great, some did not do as well, but all show the enthusiasm of the entrepreneur. Disclaimer: I am sharing what I thought of the presentations and of the startups ideas and business models; this is a very subjective digest, go visit these sites and make up your own mind.

1. Goutez (food for friends). They provide an on-line market place to buy local food products. Lots of people tried to be on-line food resellers, but only a fraction is still alive. I don’t know whether there is a market large enough to have a sustainable business here.
2. Communote. They propose an enterprise microblogging platform. Basically, a secured place where people can collaborate and share info. It looks pretty slick, and it has already a few customers. But having a Twitter for enterprise might not be enough. They had quite a number of questions regarding their differentiation with respect to other enterprise collaborative platforms. Also, may I ask what if GoogleWave goes enterprise?
3. Graph.me. Good presentation on a platform that enables users to build up their own poll, which they ask friends or social network members to answer (Facebook, MySpace). Business model is to sell the resulting data pool to marketing research. Neat idea. Obvious question is the privacy problem.
4. CaptchaAd. Propose a video ad CAPTCHA. Instead of your usual textual CAPTCHA, a short ad video is played and the used must answer a simple question (e.g., what was the brand of the car in the video?) to prove she is not a spambot. Clever idea, but will the users enjoy watching 10 seconds of video ad to fill in a form?
5. Red Panda. Intentional browsing add-on for Firefox: it instantaneously shows on a side-bar links (news, product reviews, Wikipedia articles, tweets, etc) that are relevant to whatever web page you are currently displaying. Very cool. Business model is targeted ad.
6. intelliAd. They have a web platform to optimize SEM campaign, e.g., determine the best bid for a keyword to optimize CPI. Easy setup, nice GUI, these guys are flying with 20 customers and are looking in expanding in the US. Very solid product and business plan, a success in the making.
7. Vicommerce.com. They provide a layer on top of video players that is used to define clickable area by the on-line resellers. This results in a very entertaining on-line shopping experience. They already have some major customers, solid business plan.
8. Getyourguide.com. A platform to get travelers and local activity providers together. Nice but is that enough differentiation with Yahoo! travel and Tripadvisor, to name only two?
9. Directededge.com. They provide a user recommendation plug-in to businesses. Based on the fact that 20% of Amazon’s revenue comes from user recommendation click-throughs, this is definitely a good idea. The product is still in an early stage, stay tuned.
10. SnipClip.com. They aim at monetizing brands on social networks (Facebook, MySpace), which are known to have a very low clock-through rate. The idea is to sell branded virtual goods (mostly media). Creative, let’s see whether the social network community will bite.
11. Terminii. Propose a web-based appointment services for small and mid-size business. Definitely useful. Disastrous presentation: the presenter stopped his talk because of slides issue. Mike Butcher, the host of the event, did a great job to bring back the speaker and let him explain his business.
12. Valuescope. A news aggregator filtered with natural language analysis, targeted at sales and marketing. Extremely good presentation, very focused.

Mike Butcher’s top 5 picks were:

• #5: Vicommerce.com
• #4: Directededge.com
• #3: Valuescope
• #2: CaptchaAd

and his top one pick was (drum roll please):

• #1: Graph.me

Overall a very interesting day, very well organized, with a great host. It showed that Munich has talents and a good VC structure to produce a dynamic startup environment. Congratulations to the speakers and to those that came to pitch their startups!

Related posts:

1. What to see at the TechCrunch Munich event?
2. Why FPGA startups keep failing