No doubt that for the next two weeks you will find many DAC reports in blogs and corporate marketing websites. So I tried not to write yet another DAC report, with a long list of companies and products.

Instead, I have chosen to share my absolutely non-exhaustive, completely biased view of DAC. I will then publish a couple of posts focused on specific themes in the next few days.

Attendance

The 47th DAC was held June 13-18 at the Anaheim Convention Center in California. The preliminary attendance numbers are reported as follow:

  • Total full conference: 1554
  • Total exhibit attendees: 3444 (24% international)
  • Exhibitors, visitors, and guests: 2557
  • Total attendees: 6001

The final attendance numbers are usually a few percent higher.

For a fair comparison, I pulled out the preliminary attendance numbers of the past conferences. I was first fooled by the way the numbers were labeled this year –see the comments below, and a big thanks to Sean to bring me the correct interpretation. The table below shows the correct data, excluding booth staff. It shows a sharp decline (33%) of the total attendance compared to last year in San Francisco. Not having DAC in San Francisco means higher cost for most of the attendees –many of them are from the Silicon Valley–, which is clearly reflected in the attendance numbers.  But if we compare this year’s numbers with the 2008 DAC venue held at the same location, we see the same sharp decline (28%). Note the drop in exhibits-only attendees (-41% w.r.t. 2009, -21% w.r.t. 2008), not a good sign as this number captures most of the customer audience.

DAC preliminary attendance numbers (not including booth staff)

This year’s DAC comes after one of the worst recession, but looking forward to a very strong semiconductor growth in 2010 and 2011, which should eventually translate into a mildly better business for EDA. The exhibition was well attended on Monday, with a sharp decline on Wednesday –lots of people left by that time.

The buzz

With Cadence’s EDA360 campaign in the background, and the fresh acquisitions of Denali by Cadence and Virage Logic by Synopsys, it felt that IP was the buzzword of the day. IP design here, IP verification there, verification IP everywhere, the overall SoC design looked like an IP integration problem that EDA was gearing up to take on. Embedded software and ESL were also showcased by Cadence and Mentor Graphics as part of their SoC focus.

Verification

There was a booth dedicated to UVM/OVM (Universal Verification Methodology/Open Verification Methodology). These methodologies offer open and interoperable verification solutions. They both support multiple languages and simulators, and enable verification IP, so critical to SoC design. The message was well received and had a strong attendance.

Still on the verification side, new products and startups are trying to repeat the success of Certess (acquired by SpringSoft last year). Advanced formal verification tools (e.g., property checkers) are slow to find acceptance by the design community. Instead these new products and startups leverage the existing test bench and simulation methodology in place to produce better coverage or faster simulation. Notably missing in this space was NuSym, a no-show at this year’s DAC, confirming the rumors that the startup that demonstrated “intelligent” simulation two years ago is actively looking for a buyer.

The whole simulation and emulation space was strong. Mentor’s Veloce is showing impressive numbers, and is ready to take on Cadence’s Palladium. Eve will likely take notice, and this may bring it closer to Synopsys.

Magma’s Tekton offers sign-off quality multi-mode/multi-corner static timing analysis for multi-million gate circuits. The tool has been designed from the ground up, and tailored for multi-threading and distributed systems. It is a clear competitor to Synopsys’ PrimeTime, even though running PrimeTime *is* the signoff for most customers.

Design and implementation

On the P&R and backend side, nothing really stood out. Synopsys clearly gained in QoR, Mentor’s momentum with Sierra’s Olympus is still strong, and Magma keeps lagging behind, especially in runtime. Atoptech and Azuro, although showing pretty good numbers (verified at customers’), are still considered more like add-ons that comprehensive solutions. This segment looks more and more commoditized, and only the high-end (20nm and below) and 3D seem to offer new growth opportunities in that space.

Oasys, the darling of last year’s DAC, did not make as much as a splash this time, despite its recent announcement with Juniper Networks and Xilinx. Nobody question the speed and capacity of their tool, as well as the clock cycle it can achieve. But some raised concerns regarding the area of their netlists for ASIC.

On the fringe

This is the “stuff I liked that may be too small to be noticed”, even more so since two of these three companies didn’t have a booth at DAC…

Low power is still under-represented, even though power gets worse with smaller geometries, and power management remains mostly a very manual process. In that space I liked Docea Power, which can simulate system-level models to analyze power consumptions and thermal behaviors. System-level analysis can bring the biggest power savings. It also has a significant impact on the packaging, which is still a domain where conservative approaches are preferred to more cost-efficient, but riskier, choices.

A comprehensive system-level design framework is really an IDE (Integrated Development Environment) for SoC, where hardware and software can be designed together, written and simulated together, and where the HW/SW tradeoffs can easily be explored. IDEs have been used in software for a long time, but are a novelty to hardware designers. Sigasi proposes an IDE for VHDL –what Microsoft’s Visual Studio is to C++. Although this is still light-years away from a SoC IDE, this is a hint into the future of writing RTL.

We heard several claims that cloud computing is coming to EDA (or the converse?). Xuropa best illustrates that (slow) move. They provide turn-key online community solutions for the electronic design industry. Their main customers, Cadence and Synopsys, are using the services for CRM and virtual demo only. But Xuropa could become a platform that enables collaborative design in the cloud, providing secured access to a multi-vendor flows. More on this in a future post.

Last words

I felt that there was a lot of system-centric messages (best captured by EDA360), and attempts at rising the abstraction level for higher productivity. EDA vendors are forced to see the big picture –full system design, software and hardware together. But as pointed out by Steve Jones (TI) at Cadence’s Silicon Realization Luncheon, EDA is still missing out on two important parts of the SoC design. One is that customers want a first-silicon that is functionally operational, and Steve singled out the need for useable verification IP –UVM/OVM is a step in the right direction. The other is analog –mixed-signal design is the rule, and there is no good integration there.

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10 Comments on DAC 47th digest: what you missed (even if you were there)

  1. […] This post was mentioned on Twitter by Hendrik and Tony Chin, Olivier Coudert. Olivier Coudert said: New post (RT please) RT @ocoudert 47th DAC digest: what you missed (even if you were there) http://bit.ly/bQreaM #47DAC #EDA […]

  2. JimF says:

    > Total full conference: 1554
    > Total exhibit attendees: 3444 (24% international)
    > Exhibitors, visitors, and guests: 2557
    > Total attendees: 6001

    I’m confused about these numbers. The graph shows about 5000 attendees,
    which agrees with 1554+3444=4998, but assumes that none of the full
    conference attendees and exhibit attendees are the same people.
    Your figure for total attendees is 6001=3444+2557 counts exhibitors and
    exhibit attendees but excludes full conference attendees, unless the full
    conference attendees were already included in the exhibit attendee count.

    I think the graph is incorrect. It should show total attendees as 3444,
    a significant decrease over last years 5299 in San Francisco. The
    3444 exhibit attendees includes the 1554 full conference attendees.

    “Total Participants”, including booth staff, dropped from 7996 to 6001.

    http://www2.dac.com/App_Conten.....aphics.pdf
    http://www.businesswire.com/po.....ewsLang=en

  3. The attendance data is somewhat confusing. The “exhibit only” are the people that registered to the exhibit but not to the full conference, and this number excludes booth staff. “Conference attendees” are the people that registered to the full conference, i.e., the tech session and exhibits. The data in the chart do not include booth staff, and are preliminary numbers only.

  4. The press release offers these numbers

    Total full conference: 1554
    Total exhibit attendees: 3444 (24% international)
    Exhibitors, visitors, and guests: 2557
    Total attendees: 6001

    I believe that the total exhibit attendees includes total full conference attendees (it’s the only way to make the numbers work since 3444 + 2557 = 6001 which is total attendees). So I think your chart should show

    1554 full conference and 1890 exhibits only

  5. Take a look at
    http://www2.dac.com/App_Conten....._17_09.pdf
    from the prior year

    Conference Attendees: 1,962
    Exhibit-Only Attendees: 3,337
    Booth Staff: 2,697
    Total: 7,996

    I think they reported these numbers in a way to mask the falloff of about 2,000 attendees (a 25% drop from SF). What’s not in dispute from their numbers is that total attendees dropped from 7,996 to 6,001 since booth staff stayed roughly constant (2557 vs. 2697) most of the drop had to come from full conference (1962 -> 1554) and exhibits only attendees (3337 -> 1890)

  6. As you mentioned IDEs for the hardware world, though it sounds like advertising, DVT (Design & Verification Tools) Eclipse is out there since 2004, 3rd year at DAC already. You can see more details at http://www.dvteclipse.com .

  7. Olivier I asked Lee Wood at MP Associates and he e-mailed this back, which indicates that you need to update your chart.

    Hi Sean,

    The 3444 reported below includes conference and exhibit-only attendees.

    Broken down it would be
    1554 conference,
    1890 exhibit-only/free Monday
    2557 exhibitors.

    Thanks,
    Lee

  8. Ouch. Thank you for providing me with the actual attendance numbers, I will update the chart. And yes, I’d say that the press release is misleading.

  9. Chris Wilson of Nusym reports that he is now working at Jasper in blog post dated June 20 blog post on http://bugsareeasy.wordpress.c.....ification/

  10. JohnB says:

    Nice summary. From my distant perspective of reading articles and watching tweets, I’d say you have captured the main themes of this year’s DAC. Thanks for sharing the details and your color on the conference.

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