Xilinx announced that it signed a multi-year strategic licensing agreement to use Oasys’ synthesis. What does that mean for the FPGA and EDA community?

Oasys’ product, RealTime Designer, is claimed to be 10x-60x faster than the competition. Among other things, it uses AIG-based optimization. This technology is best illustrated by UC Berkeley’s ABC synthesis: several FPGA startups reported that ABC boosted significantly the speed, capacity, and quality of their synthesis engines. No question that Oasys’ synthesis is competitive, at least in the FPGA world.

Xilinx is an investor into Oasys, and it has been toying with their synthesis technology for at least a year, so it’s not like they just discover each other. Xilinx has to close a software technological gap with respect to its closest competitor, Altera, and a fast, high capacity synthesis will certainly help.

Synthesis speed is key here. Until recently FPGA design was mostly an iterative process: synthesize, simulate, and debug (i.e., change in the RTL) until the performances and functionality of the design were satisfactory. That trial-and-error approach becomes impractical as the size of FPGA devices is increasing to the point that one single iteration takes hours, if not a day. Having a 10x speedup in synthesis means you can restore that familiar design iteration for a few more years.

Verification has become a bottleneck in FPGA. Simulating is used and will still be used in the future. But FPGA’s complexity requires a more complete verification methodology, like formal verification. However formal verification has trouble addressing optimization techniques heavily used in FPGA synthesis, like retiming and state re-encoding. An ABC-like optimization engine comes with a built-in formal verifier that can check independently the correctness of every incremental optimization steps performed during the optimization run. The correctness of the resulting netlist comes with a very high degree of confidence, and only the RTL description needs to be simulated.

Xilinx’ customers will benefit from that technology, and catch up with Altera’s synthesis. As for the EDA vendors selling their own FPGA synthesis, they all use or will use some flavor of AIG-based optimization. Differentiation will be done on the smartness of the high-level optimization –datapath, IPs–, the user experience (GUI), the integrated verification environment (still to be demonstrated), and of course the bottom-line: QoR –clock cycle, area, and power. The race is on.

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7 Comments on Who should worry about Xilinx and Oasys partnership?

  1. […] This post was mentioned on Twitter by Olivier Coudert, Olivier Coudert. Olivier Coudert said: New post RT @ocoudert Who should worry about Xilinx and Oasys partnership? http://bit.ly/bSgpjb […]

  2. Gary Dare says:

    Obviously, the Big 3 EDA firms’ value-added solutions have been put on notice. Synthesis is close enough to the core business of Xilinx (selling silicon) that they chose to make a strategic investment rather than have Oasys as yet another BYOB partner (see: Xilinx ESL Initiative).

  3. What’s your source on Xilinx investing in Oasys a year or more ago?

  4. Xilinx invested in Oasys, according to a Xilinx source. And Xilinx has been experimenting with Oasys’ synthesis technology for at least a year, according to another Xilinx (R&D) source.

  5. I wonder if the other announced clients, Juniper and Renesas, are also investors. It would put a different complexion on those relationships.

  6. Paul van Besouw Oasys has categorically denied an investment by Xilinx, Juniper, or Renesas in an interview I will publish this month.

  7. Interview with Besouw up at http://www.eetimes.com/electro.....gn-Systems

    Q: It has been reported that Xilinx is an investor in Oasys? Is either Xilinx or Juniper an investor in Oasys? Are any of the executives of either firm an investor in Oasys?

    Juniper and Xilinx are customers and not investors. Neither has taken an equity stake in Oasys. None of the executives at Juniper or Xilinx is an investor in Oasys.

    Juniper licensed our RealTime Designer software to use in its design flow. Xilinx licensed the Oasys Chip Synthesis technology and is modifying it to support FPGA designs; it will have the Xilinx brand.

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