Comments on: What you need to know about EDA360

By: Gary Dare

Gary Dare — Thu, 03 Jun 2010 21:21:12 +0000

Tom – I would agree that Olivier’s point would apply to peripheral IP components. Having seen such cases myself …

By: tomacadence

tomacadence — Thu, 03 Jun 2010 21:03:05 +0000

Olivier, thanks for your concise summary of the EDA360 vision. I have a question regarding your comment that “the cost of IP integration is often comparable to the cost of developing a new IP.” This doesn’t seem to be the case for embedded processors. I imagine that it is the case for many internal functions that are not well designed or documented for reuse.

But what interface (USB, etc.) IP? If its cost is too high, is it because of people wanting to add special features, people mucking around with the protocol itself, lack of on-chip bus connection on the “back side” or other reasons?

Tom A.

By: Olivier Coudert

Olivier Coudert — Thu, 03 Jun 2010 11:17:21 +0000

Hi Gary,

By commoditized I meant the following. Let’s assume that EDA moves up to system-level design. Then it’s all about HW/SW and IP+cores integration and verification. Most of the HW will be IPs, RAMs, cores, etc, i.e., pretty much picked up from the shelf. There will be still some logic that needs to be synthesized (soft RTL IPs, controllers, etc), but this will be pretty small compared to today’s typical IC. For a provider of an apps-ready HW/SW platform, it would make sense to focus on its core value (the platform architecture) and rely on 3rd party for the implementation (synthesis + P&R). Thus synthesis + P&R will be handled by HW service companies. That part of the flow will no longer be the bread-and-butter of the EDA industry.

By: Gary Dare

Gary Dare — Wed, 02 Jun 2010 03:20:51 +0000

I have similar impressions, Olivier, but may differ in a couple of points. For one, IP integration does not necessarily commoditize RTL synthesis and P&R. The resulting hardware designs will still differ enough to need P&R. To get there, the synthesis could occur at either RTL or ESL, depending on the IP. Duolog’s response was probably the first one in the dialogue that Cadence has instigated, with Dave Murray & Co. establishing where their technology sits in an ecosystem described by EDA360. In Cadence’s own document, they emphasized areas where their company has existing products (not usually by name) or a new one, the OIP. What struck me was the lack of emphasis on ESL, which is where I expect find the pivot point for HW or SW implementation, or HW/SW co-design (e.g., Space Codesign). The contrast between Apple iPhone and Google Android was relevant to that, since Apple requires your app to fit a fixed hardware platform (and probably different if you port it to AppleTV or the iPad) while Google Android, you port to the OS but the final hardware/software support may vary, since Android is envisioned for other uses besides mobile smartphones. In some high performance scenarios, you may need to implement some kernel and even middleware in hardware rather than software. In that case, you may be creating the hardware with more commodity types of EDA tools but to get there, need value-added tools at higher levels all the way to software.

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