Cadence unveiled EDA360 in April. Now that I found the time to read its 28-pages white paper, I can finally comment on it.

EDA360, John Bruggeman’s brainchild, is a manifesto that promotes a vision for the future of EDA. In a nutshell, it states the following:

  • So far EDA has been providing the tools to IC creators: design, implement, and verify ICs.
  • With the development cost of 32nm SoC reaching $100M, only a handful of semiconductor companies will still create ICs in the next future.
  • With modern consumer electronics fueled by apps-based model, electronic design is moving from a hardware-first to a software-centric industry.
  • Future SoC will be designed top-down, with software and apps requirements driving the integrations of IPs, DSPs, GPUs, CPUs and cores (ARM, MIPS, x86, etc).
  • EDA needs to provide the environment for integrating and optimizing software and hardware resources.

One can disagree with some figures of EDA360’s white paper (e.g., today’s cost of SoC software, placed at 50% of the total SoC development cost, which looks overstated). One can argue that this document states the obvious –that consumer electronics are differentiating with the end applications, which is more and more software dependent, which means EDA needs to focus more on the software aspect if it wants to stay relevant.

But that would not give justice to this document. EDA360 is a detailed, well articulated, and viable vision of what EDA should be. It is a call for action that can revitalize an industry that has been looking for new areas of growth.

EDA’s main value proposition must follow its customers’ evolution. Semiconductor companies are moving from silicon to system companies, which provide application-ready hardware/software platforms, targeted for a precise market within a narrow time-to-market window.

The best example is the evolution of mobile phones. It started with heterogeneous HW/OS/SW devices, all proprietary and hardware centric. Then the iPhone came in 2007, providing a HW+OS environment with a SDK (Software Development Kit) for developers in 2008, together with the App Store and its 70/30 seller/store profit sharing model. As for May 2010, the App Store offers 200,000+ apps and received over 4B downloads, and it produced a Q1’10 revenue for Apple estimated at $150-225M. The next step was Google that released Android OS for mobile devices as open source in 2008. As for May 2010, there are 17 manufacturers proposing mobile phones built on the Android platform, and 12 offerings for tablets and e-readers. The semiconductor companies providing the hardware are really delivering complete Android-enabled, apps-ready, HW/SW systems.

So where does that leave EDA? EDA already started to address some of the issues. HW/SW simulation, virtual prototyping, IP reuse, verification IP, and ESL/C-flavor synthesis have received significant investments by Cadence, Mentor, and Synopsys. Synopsys acquisition of Vast (virtual prototyping) and CoWare (ESL) was not as noticeable as Cadence’s acquisition of Denali, but it participates of the same logic. Cadence’s Open Integration Platform was announced early May, and intends to grow an ecosystem that will help realizing EDA360.

Still, we are far from an integrated development environment (IDE) for SoC, which would meet EDA360’s vision. For instance, IP reuse is still elusive –the cost of IP integration is often comparable to the cost of developing a new IP.

I don’t know whether EDA will meet the challenge of an environment where the software application drives the cores selection and power management, where IPs are selected according to some cost/performance tradeoffs, where the different hardware components are integrated seamlessly, and where the verification of the software together with the hardware is done incrementally. I don’t know whether this will result in moving from a $5B to a $25B industry. But I applaud a strong vision that gives a new roadmap for the future of EDA. It will certainly impact the industry. Already we see some EDA vendors espousing EDA360’s message, like Duolog, and Cadence’s acquisition of Denali shows it is serious about fulfilling the vision. Also if the SoC’s silicon results mostly from integrating IPs and cores, RTL synthesis and place & route will be commoditized. Only vendors able to provide HW/SW integration and verification will emerge as the next leaders.

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5 Comments on What you need to know about EDA360

  1. […] This post was mentioned on Twitter by harrytheASICguy, Olivier Coudert. Olivier Coudert said: New post: "What you need to know about #EDA360" #EDA […]

  2. Gary Dare says:

    I have similar impressions, Olivier, but may differ in a couple of points. For one, IP integration does not necessarily commoditize RTL synthesis and P&R. The resulting hardware designs will still differ enough to need P&R. To get there, the synthesis could occur at either RTL or ESL, depending on the IP. Duolog’s response was probably the first one in the dialogue that Cadence has instigated, with Dave Murray & Co. establishing where their technology sits in an ecosystem described by EDA360. In Cadence’s own document, they emphasized areas where their company has existing products (not usually by name) or a new one, the OIP. What struck me was the lack of emphasis on ESL, which is where I expect find the pivot point for HW or SW implementation, or HW/SW co-design (e.g., Space Codesign). The contrast between Apple iPhone and Google Android was relevant to that, since Apple requires your app to fit a fixed hardware platform (and probably different if you port it to AppleTV or the iPad) while Google Android, you port to the OS but the final hardware/software support may vary, since Android is envisioned for other uses besides mobile smartphones. In some high performance scenarios, you may need to implement some kernel and even middleware in hardware rather than software. In that case, you may be creating the hardware with more commodity types of EDA tools but to get there, need value-added tools at higher levels all the way to software.

  3. Hi Gary,

    By commoditized I meant the following. Let’s assume that EDA moves up to system-level design. Then it’s all about HW/SW and IP+cores integration and verification. Most of the HW will be IPs, RAMs, cores, etc, i.e., pretty much picked up from the shelf. There will be still some logic that needs to be synthesized (soft RTL IPs, controllers, etc), but this will be pretty small compared to today’s typical IC. For a provider of an apps-ready HW/SW platform, it would make sense to focus on its core value (the platform architecture) and rely on 3rd party for the implementation (synthesis + P&R). Thus synthesis + P&R will be handled by HW service companies. That part of the flow will no longer be the bread-and-butter of the EDA industry.

  4. Olivier, thanks for your concise summary of the EDA360 vision. I have a question regarding your comment that “the cost of IP integration is often comparable to the cost of developing a new IP.” This doesn’t seem to be the case for embedded processors. I imagine that it is the case for many internal functions that are not well designed or documented for reuse.

    But what interface (USB, etc.) IP? If its cost is too high, is it because of people wanting to add special features, people mucking around with the protocol itself, lack of on-chip bus connection on the “back side” or other reasons?

    Tom A.

  5. Gary Dare says:

    Tom – I would agree that Olivier’s point would apply to peripheral IP components. Having seen such cases myself … 🙁

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