As was said above and is pretty much common knowledge, an approach that let’s your customers integrate your tool into their current flow works better than one that makes them change altogether. RTL synthesis was revolutionary, but Synopsys started by re-optimizing netlists before RTL, which allowed them to get into the design flow. That gives Tier Logic an advantage.

The comment about IP and libraries is also very relevant. FPGAs are SoCs and they require the same types of IP. Who’s going to develop them? Perhaps this would be a good opportunity for open source IP.

As a company, you don’t have to be better in all these areas, just enough to get your factor up to at least 5x.(Say Tabula has 2.5x in hardware…that is great…now all they need is get together another 2x to be compelling…assuming the other factors are competetive.

For example, do the new companies have a strategy for IP&Libraries? If you look at X&A these days, that is becoming a distinguishing factor…as much as the hardware or synthesis&P&R software.
The need is for an infrastructure of IP&Libraries that are inexpensive and easy to use…shall I say it?…like software!
alan

the company was registered in 2003 but it didn’t raise any seed funding until Oct 2005 and VC funding until July 2007, so in real terms, we’ve been going a lot less long than that. You’re correct that our architecture doesn’t require anything radical in terms of tools. That helps a lot when it comes to bringing tools to market of course.
Cheers,
Paul.

Thanks for the info. I must say, that’s a very low figure for a FPGA company that has been in existence for 7 years.
As for the software, it is indeed a key component often overlooked by FPGA startups. In the case of Tier Logic, the flow is quite simple –Mentor’s Precision + Tier Logic’s mapping and P&R. As I replied to Brian, I don’t think that your architecture created any issue –no exotic technique required.
Best of luck for the future!

This post was mentioned on Twitter by ocoudert: New blog @ocoudert “Can Tabula and Tier Logic be successful?” http://ow.ly/1qeCA2 #FPGA (RT please)…

I don’t know about their back-end tools. But Tier Logic’s architecture shouldn’t be a problem for P&R.

Tabula, that’s another story. Assuming the synthesis forces the folds (i.e., P&R is not allowed to modify the folds), then it’s doable. But synthesis is extremely challenging. Yes, taking advantage of the architecture and “routing” a critical net through several folds at the same (x,y) coordinate will certainly result in a very high-performance implementation. I have seen a number of exotic synthesis systems, and one that can fully exploit time multiplex with placement is out of the ordinary. Tabula’s architecture is nothing short but groundbreaking, yet I am waiting to hear about the software tool suite. Lots of FPGA startups failed because their software were not good or mature enough.

Yes, change is hard, and that is another reason why Tier Logic is better positioned. There is nothing unorthodox in their flow. And that timing-invariant FPGA to ASIC migration will be key.