The past two weeks were pretty interesting if you follow FPGAs. Yes, Xilinx and Altera kept upping their target to Wall St., but that is not where the excitement came from. It came from the recent announcements of two startups, both created in 2003 and heavily funded. Tabula released its long-awaited device, which goes by the sexy name of “Spacetime”. And Tier Logic left its stealth mode this week to announce its own device, “TierFPGA”.

The dominant factor in classical FPGA architecture is the interconnect: most of the die area is taken by the wires and the interconnect switches and muxes. If you can somehow reduce the area dedicated to interconnect, you can augment the logic density and lessen the cost of the device. Tabula and Tier Logic pitch a 3D architecture to address the interconnect bottleneck, albeit in very different flavors.

Tabula innovative design is based on its ability to reconfigure itself, up to 8 times with a clock running at 1.6GHz. At each cycle a cell can change its functionality, its latch configuration, and its interconnect. The time-multiplexing increases the amount of logic that can be fit on the same area. It is like having 8 layers (or “folds”) of cells stacked on top of each other along a time axis, with very short connection between cells at the same (x,y) coordinate but in two adjacent folds. At each cycle one jumps to the next fold and feeds the new configured logic with the results of the previous fold. Tabula claims they increase the logic density by 2.5x compared to classical FPGA architectures.

Tier Logic’s design idea is to place the SRAM cells that configure the interconnect muxes on top of the routing layers, instead of having them distributed throughout the logic die area. Doing so leaves more room for logic cells, increasing the cell density by about 50% according to the company. The design flow will not throw anybody off: it uses Mentor’s Precision for synthesis, and is followed by Tier Logic’s mapping and P&R.

A big plus touted by Tier Logic is the ability of moving painlessly from their device to an ASIC. Simply replace the interconnect configuration SRAM cells at the top with metal, and voila, you obtain an ASIC with no change in timing. This is a simple, predictable process: it takes about 4 weeks to go from the SRAM configuration to a top-layer mask, and you do not need to go through a timing closure flow again, which means a non-recurring engineering cost of about $50k. This is a real bargain when you consider that moving from FPGA to ASIC usually requires a redesign that can take as long as 9 months.

So who of Tabula and Tier Logic is best positioned to challenge the duopoly Xilinx/Altera?

Tabula made it clear that they are aiming at the high-end of the FPGA market. There are a number of FPGA startups that targeted the same niche, and none survived. One reason is that it is easy for Xilinx and Altera to increase the size of their device, by simply moving to the next technology node. Tabula’s design is innovative and pushes the limits, but how far is too far? It is unclear whether the company can deliver the design tools to match their device’s challenges –they went through a complete reset a few years ago, replacing the whole software team. Verifying a device that can reconfigure itself 8 times in a loop may be another challenging problem. Increased density is obtained by continuous reconfiguration, which means extra power consumption: is it still an acceptable tradeoff? Last but not least, with 100+ people in the US, it is a well-known fact in the Silicon Valley that Tabula burns cash fast, and their funding of $106 millions so far is about to come short.

Tier Logic’s FPGA can reduce the cost of the device for the same density. But their compelling value proposition is really their FPGA to ASIC translation. This is what Altera’s HardCopy was supposed to be, a seamless and risk-free migration from FPGA to ASIC. For anybody that wants to design an application and then migrate to a low/medium volume ASIC production, this could be the most cost efficient solution. I do not know the inside story regarding the financial aspect, but their business proposal looks more solid.

So who do you think has a chance here? Let’s meet again in 3-4 quarters and see how the two companies are doing.

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10 Comments on Can Tabula and Tier Logic be successful?

  1. Olivier, great post and analysis. What’s your take on their back-end tools? Issue? Non-issue?
    You raise good points in this and your related posts on FPGA startups. I worked with Achronix for a while and was impressed with their high-performance differentiation but is it enough?
    Part of me thinks change is hard in general. The other part of me thinks that FPGAs simply because of their inherent flexibility are poised to become the dominant design choice in the future.
    There has to be some reason VC money is nurturing all these interesting new ideas and perhaps that has something to do with it.

  2. Hi Brian,

    I don’t know about their back-end tools. But Tier Logic’s architecture shouldn’t be a problem for P&R.

    Tabula, that’s another story. Assuming the synthesis forces the folds (i.e., P&R is not allowed to modify the folds), then it’s doable. But synthesis is extremely challenging. Yes, taking advantage of the architecture and “routing” a critical net through several folds at the same (x,y) coordinate will certainly result in a very high-performance implementation. I have seen a number of exotic synthesis systems, and one that can fully exploit time multiplex with placement is out of the ordinary. Tabula’s architecture is nothing short but groundbreaking, yet I am waiting to hear about the software tool suite. Lots of FPGA startups failed because their software were not good or mature enough.

    Yes, change is hard, and that is another reason why Tier Logic is better positioned. There is nothing unorthodox in their flow. And that timing-invariant FPGA to ASIC migration will be key.

  3. Hi Olivier,
    thanks for the insightful blogs – very interesting. I thought you’d like to know, in answer to your question towards the end, that we’ve spent just under $20M so far and are ready to take designs today. You’re quite right about FPGA Startups and tools – there have definitely been more that failed because of tools than silicon. We have tools in production release today, and although we wouldn’t claim that they have all the bells and whistles of Xilinx or Altera, the algorithms are sound and the QoR is very good. If potential customers want to register on our site, they can download the tools and try them out.

  4. Social comments and analytics for this post…

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  5. Hi Paul (note: Paul is the VP Sales & Marketing of Tier Logic),

    Thanks for the info. I must say, that’s a very low figure for a FPGA company that has been in existence for 7 years.
    As for the software, it is indeed a key component often overlooked by FPGA startups. In the case of Tier Logic, the flow is quite simple –Mentor’s Precision + Tier Logic’s mapping and P&R. As I replied to Brian, I don’t think that your architecture created any issue –no exotic technique required.
    Best of luck for the future!

  6. Olivier,

    the company was registered in 2003 but it didn’t raise any seed funding until Oct 2005 and VC funding until July 2007, so in real terms, we’ve been going a lot less long than that. You’re correct that our architecture doesn’t require anything radical in terms of tools. That helps a lot when it comes to bringing tools to market of course.

  7. Thanks for the pertinent analysis!
    My cut this time around is that success will still be defined by giving a 5-10x “improvement factor” across hardware, software, IP&Libraries, support, and pricing&delivery.

    As a company, you don’t have to be better in all these areas, just enough to get your factor up to at least 5x.(Say Tabula has 2.5x in hardware…that is great…now all they need is get together another 2x to be compelling…assuming the other factors are competetive.

    For example, do the new companies have a strategy for IP&Libraries? If you look at X&A these days, that is becoming a distinguishing factor…as much as the hardware or synthesis&P&R software.
    The need is for an infrastructure of IP&Libraries that are inexpensive and easy to use…shall I say it?…like software!

  8. What would be compelling is a significant reduction in compile (synthesis + P&R) time as a result of the architecture. I can imagine that the complexity of compile may be quite long for the Tabula approach, however, it might inherently be suited for multiple processors (8?). Turning an 8 hour compile into 1 hour would be a big deal for the debug loop. Also, perhaps incremental changes could be isolated to a single layer resulting in quick fixes. All speculation of course.

    As was said above and is pretty much common knowledge, an approach that let’s your customers integrate your tool into their current flow works better than one that makes them change altogether. RTL synthesis was revolutionary, but Synopsys started by re-optimizing netlists before RTL, which allowed them to get into the design flow. That gives Tier Logic an advantage.

    The comment about IP and libraries is also very relevant. FPGAs are SoCs and they require the same types of IP. Who’s going to develop them? Perhaps this would be a good opportunity for open source IP.

  9. anonymous coward says:

    Tierlogic folded today!!

  10. Actually, they closed the doors on July 16 –see RIP Tier Logic. Too bad, I think they had a good technology and a compelling story.

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