Yes, did you feel it? No, I am not talking about the two earthquakes that I felt last week in San Jose, shaking the buildings, and leaving people with that weird feeling that they just experienced a whisper of the Big One to come. No, I am talking about the tremor in the US economy. And, closer to me, in the EDA ecosystem.
After about a year of seeing a desolated EDA landscape, littered with startups that could not find the money to survive to the next decade, or with promises that faltered as the semiconductor industry was hit hard with inventories it could not clear, the beginning of 2010 is suddenly looking brighter. Well, not as bright as I would like it to be, but there is definitely a sense of revival.
The semiconductor industry is announcing better-than-expected numbers for CY09Q4, and the recent Consumer Electronic Show (CES) led new expectations for exciting products that should be available within the year. How will this impact EDA? If impact there is, it will not be immediate, as many of its customers are still holding on their investments for the rest of the year, since most of their designs can be done with their current flows and tools. But, as pointed out by Richard Goering, CES showcased the hot products to come, and some will definitely require EDA tools to step up. Whether it is tablet PCs, ever more powerful mobile phones, 3D-TVs (over-hyped, if I may say so), USB 3.0, or wifi-enabled cars, there are plenty of avenues where mixed signals, low power, packaging, and high-capacity SoC design and verification tools can shine.
These are all familiar topics, but CES stressed the need for better, automated, and scalable solutions.
- Mixed signals will help Cadence –Synopsys does not have a credible solution there, and Magma is still too young in this market to push its Titan offering, regardless of its technical merits.
- Low power will be a leveled field, because there is no one-vendor comprehensive solution covering all its many facets; e.g., CPF/UPF support (Cadence and Synospys–Mentor–Magma respectively); RTL-level low power synthesis, which requires complex IP or/and manual architecturing; power-efficient clock tree synthesis, best done by Azuro and Mentor’s Olympus; and last but not least, low power verification, still led by Cadence’s Conformal.
- Early packaging estimation will be an interesting challenge –table PC and mobile phones require very thin, heat-dissipating, robust devices. Mentor and Cadence should capitalize on some of their technology and experience there.
- Large SoC design and verification is becoming more acute. Synospys and Mentor look positioned to make a move against an aging First Encounter-based Cadence solution.
It is still difficult to find money to finance new ventures or keep existing startups alive, so predicting what will come from startups is quite difficult for 2010. We will surely see whether Oasys, with its promise of 10-50x larger and faster synthesis, are for real. We will see whether ATopTech can separate itself from the increasingly commodity-like backend offering. We may see whether ESL or some flavor of C/C++-based hardware design environment can help addressing SoC challenges –for designing and verifying both the silicon and the software.
There is a window of opportunities driven by a recovering consumer electronic market, where EDA can demonstrate that innovation and responsiveness to the next technological challenge does pay off. Let the game begin.