ICCAD’09 was a fairly good vintage. It started Monday morning with an excellent keynote from Hamid Pirahesh about cloud computing. The same day in the afternoon, a more EDA-focused discussion was initiated by Jim Hogan and Paul McLellan (slides can be found here), asking the question “What EDA needs to change for 2020 success?”

Paul rightly emphasized three trends. The first one is well know: the continuously rising cost of IC designs, about $50M for today’s 45nm node. The second trend is that the fastest growing part of the design cost is software –more than half of the overall cost, Paul even claiming close to 2/3 of the overall cost. The third trend is an increasingly fragmented consumer market: the number of end products goes into the 10’s of billions, but these products are declined in many more different kinds, which means that most of them are shipping in smaller individual volumes.

units_versus_time_and_market_size

Source: Morgan Stanley, Economy + Internet Trends, Web 2.0 Summit, San Francisco, Oct 2009.

This is bad news for EDA as we know it: the rising cost of design can no longer be justified if the number of units does not grow fast enough (a $50M chip starts to make sense only if it is produced for 250M units and more). Also EDA has been slow to climb up the food chain and proposes solutions for software design, which dominates the overall chip design cost.

Rising IC design cost and smaller number of units is the call for FPGA to growth even faster. Mobile applications require FPGA to do much better in terms of power consumption, but this is a hot topic (no pun intended) drawing a lot of attention and investment, and some competitive solution will emerge in the next few years. So EDA, which makes its bread and butter on IC design, should better re-align its growth strategy on software, embedded systems, HW/SW co-design, and verification. Else EDA will continue to shrink to only service the few that can still afford chip design.

The end product, as a SoC, is a puzzle where the designer mostly assembles existing cores and IPs, and decides of the tradeoff between the software and hardware parts, based on flexibility and cost factors.

I see two strong needs that EDA could build its growth on. One is functional validation of the whole system –software plus hardware. EDA has started to address the issue, even though it is still short of proposing a scalable and automated environment. To functional validation, I would also add functional flexibility: how much of the behavior can be upgraded thanks to the software part? The other need is a design navigator that would estimate the speed, area, power consumption, and cost of a SoC by exploring alternatives between cores (ARM, MIPS, etc), IPs, FPGA, and software.

Last but not least, the eternal question of an EDA serving a $250B semiconductor industry, but making less than $5B. The time-based license model has only served the interests of the semiconductor companies, to the expenses of R&D investment in EDA. Claiming a lack of innovation in the EDA industry is sometimes fair, but EDA should also innovate in business solutions instead of cannibalizing itself by cutting costs to only survive another quarter. The semiconductor industry needs a healthy EDA if it wants to address the system-level design challenges of the next 10 years. Unless, of course, a new player coming from the software world with the experience of scalable systems signs the death of the EDA industry as we know it.

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12 Comments on What EDA needs to change for 2020 success?

  1. PitchMonk says:

    Olivier,
    Thinking that EDA problems can be solved just by focusing on technology is a fallacy. Fundamentally, EDA has to change the business models. It has been amply proven that EDA is not a separate industry but an extension of semiconductor industry. Attaching mainstream products (products that generate max revenues) to a single semiconductor company by customizing the solution is a way to increase the value and hence increase the overall worth. In an environment of shrinking ASIC starts and greater risk in building ASICs, EDA business model has to take more responsibility in terms of design outcomes. Providing tools and walking away is not an option for EDA anymore. This is MHO.

  2. That is a pretty strong statement, and there is a lot of truth in what you are saying. Yes, EDA needs to change the way it does business with the semiconductor companies. However, as long as the EDA industry does not include software design in their solution, the outlook for growth will not look good. EDA will keep being an extension of the chip design industry, fragmented for the purpose of keeping a cheap access to the products, but without the necessary revenue for innovation to thrive. If you look at other software industries, you will see that the outsourcing is not as aggressive as it has been in EDA. The reason is that EDA companies, to stay in business, have to cut their cost to the bone. This is not a good long-term growth model. Let’s have EDA focus on the problems that will generate the revenue it needs, i.e., software design, SoC architecture,SoC verification.

  3. PitchMonk says:

    Olivier,
    Sorry for expressing strong sentiments. I am a victim of all the foolish decisions that EDA industry has taken in the past and I am still suffering for doing my job faithfully. You are correct in the sense that we still have to focus on the technology to generate value, but a business model can destroy all the value. That is my point. Another thing is, if EDA is truly an extension of semiconductor industry, it is time to accept and move on. For example, Synopsys signed a big contract with Intel couple of years ago. I will expect that they are customizing their solution for Intel that no other company can penetrate Intel in the foreseeable future. In other words, come next deal time, they can probably show this value and take a larger revenue share. I used to be with a company, where high-end features used to be subsidized for all the customers all the time. Packaging was never done according to the features, and there was no sales discipline to maintain the value of the advanced features. I am sure that the practice continues from what kind of information I am receiving.

  4. If Synopsys becomes the CAD department for Intel then that is simply the end of Synopsys as we now know it. Intel has lured many EDA companies into Intel-specific tool flows and features that no other company would ever use.

  5. If SNPS (and CDN and MENT) are lured to bind their future on some specific ASIC house (Intel, TI, ST, Infineon, you name it), then EDA will keep shrinking and let an open field for other industries (including the customers themselves!) to address the software design/verification and SoC “assembly” challenge. As pointed out before, EDA needs to change its business practices if it wants to have enough R&D investment to be considered a serious player in the system-level design. I hope we will see a quick consolidation so that EDA can speak with a less fractionated voice –competition is good, but EDA has been cutting itself to survive price pressure, and it cannot only rely on startups to bring in innovation.

  6. PitchMonk says:

    May be not the big ones. But anyone starting an EDA company, should attach themselves closely with one semiconductor company and become their full service provider. Recently, a small company called PwrLite used this strategy and successfully got acquired by Xilinx.

  7. Hi PitchMonk,
    Funny you said that, I met a couple of entrepreneurs yesterday and at some point we discussed the EDA industry. The outcome was that as an EDA startup, you better find a customer first and roll out your product partially financed by this customer. Instead of selling general-purpose product, you basically sell technology tailored to a specific customer for her specific needs –SaaS is more lucrative than license-based revenue.

  8. PitchMonk says:

    I agree with you 100%. Cadence has been dabbling with SaaS with moderate success. For SaaS to be successful,
    (1) there has to be a plethora of users (not customers). Some design stages like verification and front end design have many users. Not so in the back-end
    (2) the process has to be tool-independent. This is also true at the front-end and verification.
    (3) the tools must finish faster and has to be less expensive. Again, very much true for synthesis and verification (esp. if the block sizes are small)
    (4) IP content in customer side should be fairly small. This is where customers differ. But in general this is also satisfied
    (5) Methodology should be fairly general. This could also be satisfied fairly easily.

    The trouble with Cadence or any big company is that they prefer customers to use only their tools in the methodology. This forces SaaS to be applicable to the customers who have already chosen their tools. Now, if a customer has already chosen the tool, that means there is a perceived value in the tool. If so, then SaaS model will just erode the $$ and does nothing to the bottom line. Today, SaaS is used as a bargaining chip if the customer draws a hard line on the pricing. Some companies also sacrifice the pricing on actual tools using SaaS, but try to capture value by offering methodology services. I cant comment on how successful this business model is.

  9. Ninad says:

    Hi Olivier, very good article! My two cents…

    Semiconductor/EDA industries including language standards organizations are not being able to adopt and keep up with the advancements in software recent technologies and trends to enable asic engineers to develop complex and large designs in more efficient manner.

    I mean for example, I hate the fact that majority of professional design and verification engineers use gvim/emacs for editing code; a decent IDE (ideally open source or free) is still a dream for us. Compare what we have (gvim/emacs or any other) with top IDEs for languages like Java, C++.

    I said ‘language standards’ since I have this strong opinion about Verilog. Writing a pure Verilog does not make sense to me. And I do not see Verilog evolving by any means towards being more developer-friendly language. I cannot imagine designers writing a Verilog code by 2020.

    Documentation of Verilog and verification IPs; such an important aspect and highly overlooked by the most.

    SystemVerilog – It is nowhere close to being a good OOP language to me, it just an extension of Verilog that has concept of class.

    A lot can be discussed but semiconductor industry sure need change! IMHO.

    Correct me if I am wrong.

  10. Hi Ninad,

    Regarding the environment to write Verilog/VHDL, there are way less HW designers than C++/Java developers. So that may be one reason why Verilog/VHDL environment are trailing. But another reason is the resistance of a lot of designers to move to new platform. I am all for dumping Verilog/VHDL and move to C/C++ to describe HW. Unfortunately it’s like asking some industry to drop all their Fortran 77 libraries: they won’t, because there is too much legacy. Only companies that start from scratch with fresh people will be able to move up the HDL languages.

    By 2020 I am pretty much convinced that HW design will be based on cores with IPs you can buy off the shelves. The application software, system architecture, and full-system verification will be where there is value and a sustainable market. There will be no more full VLSI implementation, except for a handful of core manufacturers. Where EDA will be then? Absorbed by these core manufacturers, absorbed by HW service companies, transformed into a system-level design and verification industry. Or no longer present because obsoleted.

  11. VM says:

    Olivier,

    You hit the nail on the head in terms of what afflicts EDA today and how it needs to reinvent itself to be of value to the broader design community.

    I couldn’t agree more with Paul’s three trends and what struck me most is the fragmented end-market for chips not yielding high enough a volume for products. I have seen this first hand having worked with ARM and MIPS, as well as their end-users and OEM/ODMs over the years. A microcosm of an example of reversing this trend can be found in a very small company that does non-high end video games (www.zeeboinc.com). They rely on the cellphone market for their system’s BoM, as well as tapping into the economies of scale of the existing chipsets found in a mobile phone, which apparently constitutes the single largest set of silicon in a device. It’s amazing that they were able to get their product out with just $4Mill. of capital! While I have no connection with Zeebo, I thought there in lay an interesting way for other larger companies to emulate, trying to find multiple end-products for their chips.

    I too think that there’re excellent prospects for companies to go into the “design navigation” space that’d help end-users explore multiple design parameters as well as trade-off multiple/cost effective hardware/software solutions. You just cannot ignore to look at the entire puzzle of product development.

    cheers,
    VM

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