Yes, you are correct, you don’t have to write complex properties to use formal tools. This is why there are these specialized domains I describe in the post, like IP verification, or timing exception verification –note that I included CDC into timing exception verification, even though it should be more under a “timing verification” umbrella. The problem with model checking is that compared to EC, there really is a jump in terms of computational complexity (NP-complete vs. P-space complete). Even though a lot progresses have been done in that field, it still requires methods tailored to the class of problems to complete a proof.

I agree software verification is an opening for formal verification. For example a company like Coverity (which provides static code analysis solutions) is using basic SAT techniques to go deeper in the branching path analysis of C/C++. There are also other techniques (like HOL or predicate logic) used here and there for some very specific applications, but they are not about to come to us any time soon.

Post-silicon debug is a bit on the side, it uses techniques coming more from DFT than formal verification. Some successes (e.g, Dafca) show there is a market to be addressed.

Going back to software verification and the potential expansion of formal verification techniques, I believe that there is a core of software verification that could find a lot of traction. A huge, untapped market, is the verification of simple web applications (java, javascript), where the size of the code is relatively small, but the problems posed by security, privacy, and deadlocks are extremely costly (think your typical banking or on-line shopping web applications, as well as the many application like games and polls in social networks).

I just wanted to add few points on top of that
1) like Jasper, Cadences IFV(Incisive Formal Verifier) is also a good model checking Formal tool. They also have IEV for hybrid verification
2) Now a days, VIPs are playing a key role for protocol verification. Like Cadence’s OCP VIP, AXI Formal-VIP etc
3) Though model checking tool has capacity issues, but somewhat it can be solved bu “assume – guarantee” approach or other FV techmique

Regards,
Lopa

–You don’t necessarily have to write complex properties to use formal tools. Some have automated property generation capabilities, or use “canned” checks like CDC.
–Model checking has capacity limits, but it’s as much about the type of block as the number of transistors or gates.
–Software validation is a large potential growth area for formal techniques. Post-silicon debug is a new area that’s attracting interest.

Keep up the good work!

Nice blog.

-Nick