Low power is becoming more and more critical as the number of mobile and wireless applications is increasing. Battery life is a feature that can make the difference between a success and a flop. Remember the first version of the iPhone? All praised the touch screen interface, but so many criticized its poor battery life.
For mobile products, leakage power (the power consumed when the device is on but idle) has become a dominant factor, as opposed to dynamic power (the power resulting from the actual activity of the device, e.g., during a call for a cell phone). In that context, power gating is a key for extended battery life. Under some condition (e.g., the “on/off” button is pressed, or the device has been unused for some time), the device goes to sleep: it powers down most of its elements and preserves enough information to restore the state it was in before going to sleep. Under another condition (e.g., the “on/off” button is pressed again), the device powers back up and resumes its course as it was right before going to sleep.
UPF (Unified Power Format, endorsed by Synopsys, Mentor, and Magma) has been introduced to describe the power supply distribution and its control. With UPF one can specify power domains (a set of design elements that share a power supply), and a power state table that captures the transitions between the power domains. For instance it is used to describe under which conditions the device goes to sleep, under which conditions it must be powered back up, and what happens whenever the device transitions between these modes. UPF allows the designer to specify retention flops, level shifters, and isolation cells, all necessary items for multiple voltage designs and power gating. CPF, promoted by Cadence, is another format that is used to describe similar power management schemes.
Low power has been a subject of attention from chip designers and EDA for more than 10 years. Indeed, a lot of improvement has been done. New techniques have been introduced, and most are now common practices and relatively well automated –clock gating, multiple Vt cells, multiple voltages.
Despite these progresses, low power-centric design flows remain a very labor intensive process. Even if UPF/CPF can be used to describe transitions between different power modes, it is up to the designer to manually write the controller (as a FSM) that implements the transitions, and it is up to the designer to determine which information must be preserved (the retention flops) in order to resume the application to its pre-sleep state.
Also low-power designs create new challenges for functional verification. For instance, after going to sleep, the device must be able to resume without loss of information. Since the sleep and power-back-up sequences take several clock cycles, simple equivalence checking is not sufficient. Sequential verification or intensive simulation is needed. Cadence did a relatively good job in tying CPF to its Formal Verification solution (Conformal), Mentor and Synopsys have some reasonable flow for UPF, but verifying the correctness of a power state table FSM is still a very manual and error-prone process.
EDA stands for bringing automation to design flows, and low power design could use some help. In Part II, I will show how some parts of the low power design flow can be automated.
Power state table: a table that describes the transitions between power domains. Transitions are annotated with logical expressions under which they are triggered.
Retention flop: an always-on flop that shadows the state of a flop. It retains its logic state even when the primary power supply to the cell is shut off. It is used to restore the state of a device when it is powered back up.
Level shifter: cell used to allow a signal to pass from one power domain to another.
Clock gating: power-saving technique that consists of blocking the clock signal leading to flops so that flops cannot change their state. Since their states are fixed, the downstream logic will not toggle, which saves dynamic power.
Multiple Vt: multiple voltage threshold cells. A cell speed depends on its voltage threshold. The lower its voltage threshold, the faster the cell is, but the higher its leakage power. High Vt cells are used for non-timing critical parts of the circuit, while low Vt cells are used for critical paths only, so that the overall leakage power is reduced.
Multiple voltages, Voltage islands, MVDD: a component of a circuit can operate under several voltages, or components can have different operational voltage. The higher the voltage, the faster the component is, the higher its leakage and dynamic power.
Dynamic power: the power dissipated by a circuit due to its cells switching from one state to the next. It is proportional to Vdd2tr, where Vdd is the voltage supply of the cell, and tr is its transition rate (or toggle rate) per second.
Leakage power, static power: the power dissipated due to the leakage current passing through transistors. Practically it is the power dissipated when the cell does not toggle. It is proportional to Vdd exp(- Vt / T), where Vdd is the voltage supply of the cell, Vt is its voltage threshold, and T the temperature.