But the real issue on the market with these startups is that their technology DOES NOT WORK.

The reason that most of these companies have not had great announcements for huge periods of time is not because they are too happy to share their success. It is not because their customers are too secretive and dont want to disclose they use alternative FPGAs.
It is because their success is negligible or ZERO.

They are companies offering BROKEN technologies. They soon find themselves that so much is broken that they usually stay with the same process technology for too long renderring their technology obsolete (on top of BROKEN).

Why are these technologies broken? Well, the human factor is definitive. There is very little good talent left in the FPGA industry. The very few talent left are often managed by mediocre management. These few talented people often do not respond well to mediocre management. As a result, nothing works.

And why is there so very few talented managers and technical expertise? Simple, they are somewhere else writing software, in the green bzness, bio engineering, etc. Just about anywhere where there is potential for growth.

And why is everybody running away from the FPGA industry? Because even though the technology has gotten much bigger, their tools and methodology have not cought up with the growth. New methodologies have been proposed (such as hardware level C like languages) but none have solved the fundamental problem of allowing designers to code faster and more easily on a higher level of abstraction.
The future of programmable logic does not lie in X or A. It will probably be on GPU like technology offered by NVIDIA.

Thanks for this insightful comment. Let me comment on a couple of points –I will get back to your other comments in another reply–.

You are right to point out that FPGA has been moving away from the “one-size-fits-all” 4-LUT architecture, to propose a structure with more complex, still basic, blocks (e.g., adders and multipliers, bitwise operators). This is certainly a chance for innovations here, but then it is entirely dependent on the synthesis software that will be able to take advantage of such an architecture –as your comment agrees regarding Ambric, which defined the programming model before defining the silicon.

Since we’re talking FPGA software, it is clear that it is an essential component of an FPGA company’s success. It must be free –that is the model currently in use–, and it must be top-notch quality in terms of stability and QoR. Needless to say, I don’t think FPGA companies scored very well in that field. Even the two big ones have shown questionable solutions in the past 10 years. Remember the disastrous roll out of Altera’s new synthesis release in 2000-2001? The tool was simply not ready. That did cost them market share and a few big name customers (Cisco, to name only one). Altera learned its lesson and is certainly in a better position now regarding the quality of its synthesis. Xilinx’ software situation today is not great: code quality is NOT good, stability and QoR is average or below average (don’t mind me, listen to the customers feedback), and the software development team is bloated. There are new technologies being put in place, but they have still to show they can put it together and release a good synthesis solution.

Real-time and/or adaptive reconfiguration is indeed a wide open field. Again here, software is the bottleneck. Whoever will deliver a solution in that space will come from the software (synthesis/compiler) world, not from the EE FPGA world.

One trend that startups may exploit — and X and A’s product roadmaps clearly show this — has been the incorporation of more (and more types) of dedicated functional blocks. The obvious first foray into this was on-chip dedicated memory blocks. Now we see a wide range of CPU, DSP, PHY, and a whole host of other “common” blocks that are much faster, smaller, lower power, faster to develop with, and more reliable than equivalent blocks created from 4-LUTs. Matching just the right mix of these “hard” blocks with the right amount of programmable fabric is a key to success. The “one size fits all” (or, better stated, the “one FABRIC fits all”) days of general purpose FPGAs aren’t over, but with more offerings targeting specific application spaces, the overall FPGA market will continue to fragment based on application and market focus. This fragmentation opens the door for innovation — and better programmable solutions — in each individual space.

Tools (…and everyone who knows me knows I’ve been preaching this for YEARS!) are another area that is both a barrier to entry *and* an opportunity for innovation. MANY pretenders to the FPGA throne have failed, NOT because of a lack of value in their SILICON, but rather because they either a.) intro’d the silicon WITHOUT a robust toolset or b.) tried to CHARGE for tools (no one who’s even partially happy with their current FPGA solutions will PAY for tools for an unproven-in-the-marketplace device, period) . The history is clear — from the early days of MMI/AMD giving away ABEL to Xilinx dropping 5 1/2 floppies with XACT 0.1 from helicopters, NO new programmable logic architecture has ever been successful without free and freely available tools. Many failed FPGA startups have also GROSSLY underestimated the engineering cost and effort required to produce quality map, place, and route tools and the supporting timing closure and optimization tools.

In addition, synthesis, P&R, timing, and optimization tools and the algorithms behind them have been super-optimized over many, MANY years to the 4-LUT genre and for X and A architectures in particular. Companies that have invested heavily in Synopsys, Cadence, etc. tools and have spun their engineering staffs up on a specific FPGA vendor will be hard pressed to abandon that investment for an unproven start-up.

That said, the opportunities for innovation in the tools space is enormous. Celoxica set the stage many years ago with their “C-to-Gates” solution (and with 25 software engineers for every hardware bloke or bloke-ette out there, it’s a reasonable pitch!). Ambric was another company that had the right idea, but ran out of money. (Like several other commentors have noted, Ambric’s device was NOT anything at all like a conventional FPGA; it was an array of 336 32-bit CPUs). Ambric defined the programming model FIRST, then defined the silicon. They then used the open-source Eclipse IDE as the backbone for their tool. They initially tried to sell that tool (with some minor success) but understood that to really be successful, they needed to have a FREE version.

Open-source and libraries of free functional blocks have changed the game. Much like the Java, Eclipse, Linux, and other open source juggernauts, this trend will continue and accelerate. An innovative silicon architecture and tool set that can exploit this will have a decided market advantage.

So… what’s the Bob Klein vision of a programmable silicon start-up that can succeed in a market so dominated by two behemoths? First, any such contender will need to have a laser-focus on a specific niche or application space. Best-in-class hard functional blocks — or semi-hard functional blocks with some configurable parameters — tailored to the targeted application space will provide a foot-in-the-door in those spaces.

Rael-time or even ADAPTIVE reconfiguration is another huge opportunity. 1000 gates re-used 1000 times gives — well, you get the idea! The size and power advantages are obvious. The problems with parallel processing and tools for supporting multi-core devices are well known. Taking essential sequential code — and creating a silicon machine that DYNAMICALLY reconfigures to match the current set of processing requirements is one innovative solution. Finding the right balance — determining what functions demand hard blocks, which can benefit from executing in a massively parallel fashion, and which can be implemented in dynamic silicon — will be key.

Any new configurable device should NOT require any exotic process, and while innovations in structure and fabric are important, care must taken to not underestimate the power of incumbency. For example, in the programmable fabric, the SRAM 4-LUT remains king (even if just due to the huge investment in synth technology for that structure). In the case of processors, the compilers and 3rd party tools for ARM, MIPs and the like are highly developed and ubiquitous. (IMHO, another mistake Ambric made was in “rolling their own” CPU and instruction set. Using an “ARM-like” or “MIPS-esque” CPU core would have made it much more approachable and marketable even if they woulda needed to reduce that “336 CPU” number!)

An Ambric-like device, based on an ARM-lite core with free, easy-to-use tools, closely coupled with a real-time reconfigurable fabric and connected via a channel-based toroidal interconnect (an old patent of mine based on row/column “skipping”!) could rock the world!

Here are my personal opinions:

FPGA startups are a losing proposition.This is a niche market, well-protected by
1) Patents
2) The fact FPGA full-custom hardware is hard to create
3) The fact that FPGA P&R software is very hard to implement efficiently.
4) The preferred treatment, and early process access that the major FPGA manufacturers get.

Some things that might break the duopoly:
1) One of X or A screwing up on execution (hence making it a monopoly)
2) FPGA’s becoming obsolete (Don’t see that happening)

But FPGA startups will either
1) Implode because of technical difficulties
2) Be sued by either X or A for violating one of the many patents
3) Be acquired by either X or A.

My 2c

Great blog BTW