We all know that functional verification is the costliest and most time-consuming aspect of ASIC design –about 50% of the total cost, and from 40% to 70% of the total project duration. And we all know that simulation is by far the prevalent verification method, even though it is inherently incomplete due [...]
Continue reading Has formal verification technology stalled?
Yes, did you feel it? No, I am not talking about the two earthquakes that I felt last week in San Jose, shaking the buildings, and leaving people with that weird feeling that they just experienced a whisper of the Big One to come. No, I am talking about the tremor [...]
Continue reading Did you feel the tremor? The 2010 challenges for EDA
It is not quite yet the last day of the year, but two days to go is good enough to reflect on my recent blogging experience. I published my first post on September 14 of this year. Starting from scratch is always difficult, and starting a blog nowadays means you have to compete with millions [...]
Continue reading End-of-the-year reflection: what is it to blog in EDA?
Over the past week we heard good news from Xilinx and Altera, both raising their revenue targets for Q4CY09 (Q3FY10 and Q4FY09 respectively). Both of the FPGA giants are doing fine, and are poised to grow twice as fast as the semiconductor industry. The semiconductors companies [...]
Continue reading Why service companies will eat up EDA
ICCAD’09 was a fairly good vintage. It started Monday morning with an excellent keynote from Hamid Pirahesh about cloud computing. The same day in the afternoon, a more EDA-focused discussion was initiated by Jim Hogan and Paul McLellan (slides can be found here), asking the [...]
Continue reading What EDA needs to change for 2020 success?